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Side by Side Diff: src/trusted/validator_arm/gen/arm32_decode_named.cc

Issue 9960043: Finish separation of testing from sel_ldr validation. Also, automate (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 8 months ago
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1 /* 3 /*
2 * Copyright 2012 The Native Client Authors. All rights reserved. 4 * Copyright 2012 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can 5 * Use of this source code is governed by a BSD-style license that can
4 * be found in the LICENSE file. 6 * be found in the LICENSE file.
5 */ 7 */
6 8
7 /* 9 // DO NOT EDIT: GENERATED CODE
8 * DO NOT EDIT: GENERATED CODE 10
9 */ 11
10 12 #ifndef NACL_TRUSTED_BUT_NOT_TCB
11 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_named.h" 13 #error This file is not meant for use in the TCB
14 #endif
15
16
17 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_named_decoder .h"
12 18
13 #include <stdio.h> 19 #include <stdio.h>
14 20
15 namespace nacl_arm_dec { 21 using nacl_arm_dec::ClassDecoder;
16 22 using nacl_arm_dec::Instruction;
17 const char* NamedCoprocessorOp::name() const { 23
18 return "CoprocessorOp"; 24 namespace nacl_arm_test {
19 } 25
20 26 NamedArm32DecoderState::NamedArm32DecoderState()
21 const char* NamedImmediateBic::name() const { 27 : nacl_arm_dec::DecoderState()
22 return "ImmediateBic"; 28
23 } 29 , Binary3RegisterShiftedTest_instance_()
24 30
25 const char* NamedLoadMultiple::name() const { 31 , Binary4RegisterShiftedOp_instance_()
26 return "LoadMultiple"; 32
27 } 33 , Branch_instance_()
28 34
29 const char* NamedLoadCoprocessor::name() const { 35 , Breakpoint_instance_()
30 return "LoadCoprocessor"; 36
31 } 37 , BxBlx_instance_()
32 38
33 const char* NamedLoadDoubleExclusive::name() const { 39 , CoprocessorOp_instance_()
34 return "LoadDoubleExclusive"; 40
35 } 41 , DataProc_instance_()
36 42
37 const char* NamedBranch::name() const { 43 , Deprecated_instance_()
38 return "Branch"; 44
39 } 45 , EffectiveNoOp_instance_()
40 46
41 const char* NamedTest::name() const { 47 , Forbidden_instance_()
42 return "Test"; 48
43 } 49 , ImmediateBic_instance_()
44 50
45 const char* NamedStoreRegister::name() const { 51 , LoadCoprocessor_instance_()
46 return "StoreRegister"; 52
47 } 53 , LoadDoubleExclusive_instance_()
48 54
49 const char* NamedMoveDoubleFromCoprocessor::name() const { 55 , LoadDoubleI_instance_()
50 return "MoveDoubleFromCoprocessor"; 56
51 } 57 , LoadDoubleR_instance_()
52 58
53 const char* NamedTestImmediate::name() const { 59 , LoadExclusive_instance_()
54 return "TestImmediate"; 60
55 } 61 , LoadImmediate_instance_()
56 62
57 const char* NamedBxBlx::name() const { 63 , LoadMultiple_instance_()
58 return "BxBlx"; 64
59 } 65 , LoadRegister_instance_()
60 66
61 const char* NamedEffectiveNoOp::name() const { 67 , LongMultiply_instance_()
62 return "EffectiveNoOp"; 68
63 } 69 , MoveDoubleFromCoprocessor_instance_()
64 70
65 const char* NamedLongMultiply::name() const { 71 , MoveFromCoprocessor_instance_()
66 return "LongMultiply"; 72
67 } 73 , MoveToStatusRegister_instance_()
68 74
69 const char* NamedBinary4RegisterShiftedOp::name() const { 75 , Multiply_instance_()
70 return "Binary4RegisterShiftedOp"; 76
71 } 77 , PackSatRev_instance_()
72 78
73 const char* NamedBreakpoint::name() const { 79 , Roadblock_instance_()
74 return "Breakpoint"; 80
75 } 81 , SatAddSub_instance_()
76 82
77 const char* NamedMultiply::name() const { 83 , StoreCoprocessor_instance_()
78 return "Multiply"; 84
79 } 85 , StoreExclusive_instance_()
80 86
81 const char* NamedPackSatRev::name() const { 87 , StoreImmediate_instance_()
82 return "PackSatRev"; 88
83 } 89 , StoreRegister_instance_()
84 90
85 const char* NamedLoadExclusive::name() const { 91 , Test_instance_()
86 return "LoadExclusive"; 92
87 } 93 , TestImmediate_instance_()
88 94
89 const char* NamedVectorStore::name() const { 95 , Unary3RegisterShiftedOp_instance_()
90 return "VectorStore"; 96
91 } 97 , Undefined_instance_()
92 98
93 const char* NamedUnary3RegisterShiftedOp::name() const { 99 , Unpredictable_instance_()
94 return "Unary3RegisterShiftedOp"; 100
95 } 101 , VectorLoad_instance_()
96 102
97 const char* NamedUndefined::name() const { 103 , VectorStore_instance_()
98 return "Undefined"; 104
99 } 105 , Add_Rule_7_A1_P26Binary4RegisterShiftedOp_instance_()
100 106
101 const char* NamedDataProc::name() const { 107 , Rsb_Rule_144_A1_P288Binary4RegisterShiftedOp_instance_()
102 return "DataProc"; 108
103 } 109 {}
104 110
105 const char* NamedDeprecated::name() const { 111 NamedArm32DecoderState::~NamedArm32DecoderState() {}
106 return "Deprecated";
107 }
108
109 const char* NamedLoadImmediate::name() const {
110 return "LoadImmediate";
111 }
112
113 const char* NamedStoreCoprocessor::name() const {
114 return "StoreCoprocessor";
115 }
116
117 const char* NamedRoadblock::name() const {
118 return "Roadblock";
119 }
120
121 const char* NamedLoadDoubleR::name() const {
122 return "LoadDoubleR";
123 }
124
125 const char* NamedStoreExclusive::name() const {
126 return "StoreExclusive";
127 }
128
129 const char* NamedStoreImmediate::name() const {
130 return "StoreImmediate";
131 }
132
133 const char* NamedMoveFromCoprocessor::name() const {
134 return "MoveFromCoprocessor";
135 }
136
137 const char* NamedLoadRegister::name() const {
138 return "LoadRegister";
139 }
140
141 const char* NamedLoadDoubleI::name() const {
142 return "LoadDoubleI";
143 }
144
145 const char* NamedBinary3RegisterShiftedTest::name() const {
146 return "Binary3RegisterShiftedTest";
147 }
148
149 const char* NamedUnpredictable::name() const {
150 return "Unpredictable";
151 }
152
153 const char* NamedForbidden::name() const {
154 return "Forbidden";
155 }
156
157 const char* NamedVectorLoad::name() const {
158 return "VectorLoad";
159 }
160
161 const char* NamedMoveToStatusRegister::name() const {
162 return "MoveToStatusRegister";
163 }
164
165 const char* NamedSatAddSub::name() const {
166 return "SatAddSub";
167 }
168
169 /*
170 * Prototypes for static table-matching functions.
171 */
172 static inline const ClassDecoder &decode_ARMv7(
173 const Instruction insn, const NamedArm32DecoderState *state);
174
175 static inline const ClassDecoder &decode_dp_misc(
176 const Instruction insn, const NamedArm32DecoderState *state);
177
178 static inline const ClassDecoder &decode_dp_reg(
179 const Instruction insn, const NamedArm32DecoderState *state);
180
181 static inline const ClassDecoder &decode_dp_reg_shifted(
182 const Instruction insn, const NamedArm32DecoderState *state);
183
184 static inline const ClassDecoder &decode_dp_immed(
185 const Instruction insn, const NamedArm32DecoderState *state);
186
187 static inline const ClassDecoder &decode_mult(
188 const Instruction insn, const NamedArm32DecoderState *state);
189
190 static inline const ClassDecoder &decode_sat_add_sub(
191 const Instruction insn, const NamedArm32DecoderState *state);
192
193 static inline const ClassDecoder &decode_half_mult(
194 const Instruction insn, const NamedArm32DecoderState *state);
195
196 static inline const ClassDecoder &decode_extra_load_store(
197 const Instruction insn, const NamedArm32DecoderState *state);
198
199 static inline const ClassDecoder &decode_sync(
200 const Instruction insn, const NamedArm32DecoderState *state);
201
202 static inline const ClassDecoder &decode_msr_and_hints(
203 const Instruction insn, const NamedArm32DecoderState *state);
204
205 static inline const ClassDecoder &decode_misc(
206 const Instruction insn, const NamedArm32DecoderState *state);
207
208 static inline const ClassDecoder &decode_load_store_word_byte(
209 const Instruction insn, const NamedArm32DecoderState *state);
210
211 static inline const ClassDecoder &decode_media(
212 const Instruction insn, const NamedArm32DecoderState *state);
213
214 static inline const ClassDecoder &decode_parallel_add_sub(
215 const Instruction insn, const NamedArm32DecoderState *state);
216
217 static inline const ClassDecoder &decode_pack_sat_rev(
218 const Instruction insn, const NamedArm32DecoderState *state);
219
220 static inline const ClassDecoder &decode_signed_mult(
221 const Instruction insn, const NamedArm32DecoderState *state);
222
223 static inline const ClassDecoder &decode_branch_block_xfer(
224 const Instruction insn, const NamedArm32DecoderState *state);
225
226 static inline const ClassDecoder &decode_super_cop(
227 const Instruction insn, const NamedArm32DecoderState *state);
228
229 static inline const ClassDecoder &decode_unconditional(
230 const Instruction insn, const NamedArm32DecoderState *state);
231
232 static inline const ClassDecoder &decode_misc_hints_simd(
233 const Instruction insn, const NamedArm32DecoderState *state);
234
235 static inline const ClassDecoder &decode_simd_dp(
236 const Instruction insn, const NamedArm32DecoderState *state);
237
238 static inline const ClassDecoder &decode_simd_dp_3same(
239 const Instruction insn, const NamedArm32DecoderState *state);
240
241 static inline const ClassDecoder &decode_simd_dp_3diff(
242 const Instruction insn, const NamedArm32DecoderState *state);
243
244 static inline const ClassDecoder &decode_simd_dp_2scalar(
245 const Instruction insn, const NamedArm32DecoderState *state);
246
247 static inline const ClassDecoder &decode_simd_dp_2shift(
248 const Instruction insn, const NamedArm32DecoderState *state);
249
250 static inline const ClassDecoder &decode_simd_dp_2misc(
251 const Instruction insn, const NamedArm32DecoderState *state);
252
253 static inline const ClassDecoder &decode_simd_dp_1imm(
254 const Instruction insn, const NamedArm32DecoderState *state);
255
256 static inline const ClassDecoder &decode_simd_load_store(
257 const Instruction insn, const NamedArm32DecoderState *state);
258
259 static inline const ClassDecoder &decode_simd_load_store_l0(
260 const Instruction insn, const NamedArm32DecoderState *state);
261
262 static inline const ClassDecoder &decode_simd_load_store_l1(
263 const Instruction insn, const NamedArm32DecoderState *state);
264
265 /*
266 * Table-matching function implementations.
267 */
268 112
269 /* 113 /*
270 * Implementation of table ARMv7. 114 * Implementation of table ARMv7.
271 * Specified by: See Section A5.1. 115 * Specified by: ('See Section A5.1',)
272 */ 116 */
273 static inline const ClassDecoder &decode_ARMv7( 117 const NamedClassDecoder& NamedArm32DecoderState::decode_ARMv7(
274 const Instruction insn, const NamedArm32DecoderState *state) { 118 const nacl_arm_dec::Instruction insn) const {
119
120 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x00000000) && (true)) {
121 return decode_dp_misc(insn);
122 }
123
124 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x0C000000) && (true)) {
125 return decode_super_cop(insn);
126 }
127
128 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000010)) {
129 return decode_media(insn);
130 }
131
275 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x04000000) && (true)) { 132 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x04000000) && (true)) {
276 return decode_load_store_word_byte(insn, state); 133 return decode_load_store_word_byte(insn);
277 } 134 }
278 135
279 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000000)) { 136 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000000)) {
280 return decode_load_store_word_byte(insn, state); 137 return decode_load_store_word_byte(insn);
281 } 138 }
282 139
283 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000010)) {
284 return decode_media(insn, state);
285 }
286
287 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x00000000) && (true)) {
288 return decode_dp_misc(insn, state);
289 }
290
291 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x08000000) && (true)) { 140 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x08000000) && (true)) {
292 return decode_branch_block_xfer(insn, state); 141 return decode_branch_block_xfer(insn);
293 } 142 }
294 143
295 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x0C000000) && (true)) {
296 return decode_super_cop(insn, state);
297 }
298
299 if (((insn & 0xF0000000) == 0xF0000000) && (true) && (true)) { 144 if (((insn & 0xF0000000) == 0xF0000000) && (true) && (true)) {
300 return decode_unconditional(insn, state); 145 return decode_unconditional(insn);
301 } 146 }
302 147
303 // Catch any attempt to fall through... 148 // Catch any attempt to fall through...
304 fprintf(stderr, "TABLE IS INCOMPLETE: ARMv7 could not parse %08X",insn.bits(31 ,0)); 149 fprintf(stderr, "TABLE IS INCOMPLETE: ARMv7 could not parse %08X",
305 return state->Forbidden_instance_; 150 insn.bits(31,0));
306 } 151 return Forbidden_instance_;
152 }
153
154
155 /*
156 * Implementation of table branch_block_xfer.
157 * Specified by: ('See Section A5.5',)
158 */
159 const NamedClassDecoder& NamedArm32DecoderState::decode_branch_block_xfer(
160 const nacl_arm_dec::Instruction insn) const {
161 UNREFERENCED_PARAMETER(insn);
162 if (((insn & 0x02500000) == 0x00100000)) {
163 return LoadMultiple_instance_;
164 }
165
166 if (((insn & 0x02000000) == 0x02000000)) {
167 return Branch_instance_;
168 }
169
170 if (((insn & 0x02500000) == 0x00000000)) {
171 return StoreImmediate_instance_;
172 }
173
174 if (((insn & 0x02400000) == 0x00400000)) {
175 return Forbidden_instance_;
176 }
177
178 // Catch any attempt to fall through...
179 fprintf(stderr, "TABLE IS INCOMPLETE: branch_block_xfer could not parse %08X",
180 insn.bits(31,0));
181 return Forbidden_instance_;
182 }
183
184
185 /*
186 * Implementation of table dp_immed.
187 * Specified by: ('See Section A5.2.3',)
188 */
189 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_immed(
190 const nacl_arm_dec::Instruction insn) const {
191 UNREFERENCED_PARAMETER(insn);
192 if (((insn & 0x01E00000) == 0x01E00000)) {
193 return DataProc_instance_;
194 }
195
196 if (((insn & 0x01C00000) == 0x00000000)) {
197 return DataProc_instance_;
198 }
199
200 if (((insn & 0x01400000) == 0x00400000)) {
201 return DataProc_instance_;
202 }
203
204 if (((insn & 0x00C00000) == 0x00800000)) {
205 return DataProc_instance_;
206 }
207
208 if (((insn & 0x01F00000) == 0x01500000)) {
209 return Test_instance_;
210 }
211
212 if (((insn & 0x01B00000) == 0x01300000)) {
213 return Test_instance_;
214 }
215
216 if (((insn & 0x01F00000) == 0x01100000)) {
217 return TestImmediate_instance_;
218 }
219
220 if (((insn & 0x01E00000) == 0x01C00000)) {
221 return ImmediateBic_instance_;
222 }
223
224 // Catch any attempt to fall through...
225 fprintf(stderr, "TABLE IS INCOMPLETE: dp_immed could not parse %08X",
226 insn.bits(31,0));
227 return Forbidden_instance_;
228 }
229
307 230
308 /* 231 /*
309 * Implementation of table dp_misc. 232 * Implementation of table dp_misc.
310 * Specified by: See Section A5.2. 233 * Specified by: ('See Section A5.2',)
311 */ 234 */
312 static inline const ClassDecoder &decode_dp_misc( 235 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_misc(
313 const Instruction insn, const NamedArm32DecoderState *state) { 236 const nacl_arm_dec::Instruction insn) const {
237
238 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000010) == 0x00000000)) {
239 return decode_dp_reg(insn);
240 }
241
242 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000080) == 0x00000000)) {
243 return decode_misc(insn);
244 }
245
246 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01900000) != 0x01000000) && (true)) {
247 return decode_dp_immed(insn);
248 }
249
250 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000090) == 0x00000080)) {
251 return decode_half_mult(insn);
252 }
253
254 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01000000) && (true)) {
255 return DataProc_instance_;
256 }
257
258 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
259 return Forbidden_instance_;
260 }
261
262 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
263 return Forbidden_instance_;
264 }
265
266 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
267 return decode_extra_load_store(insn);
268 }
269
270 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
271 return decode_extra_load_store(insn);
272 }
273
274 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01200000) && (true)) {
275 return decode_msr_and_hints(insn);
276 }
277
278 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000090)) {
279 return decode_sync(insn);
280 }
281
314 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000090) == 0x00000010)) { 282 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000090) == 0x00000010)) {
315 return decode_dp_reg_shifted(insn, state); 283 return decode_dp_reg_shifted(insn);
316 } 284 }
317 285
318 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000010) == 0x00000000)) {
319 return decode_dp_reg(insn, state);
320 }
321
322 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000090) == 0x00000080)) {
323 return decode_half_mult(insn, state);
324 }
325
326 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000080) == 0x00000000)) {
327 return decode_misc(insn, state);
328 }
329
330 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
331 return decode_extra_load_store(insn, state);
332 }
333
334 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
335 return decode_extra_load_store(insn, state);
336 }
337
338 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
339 return state->Forbidden_instance_;
340 }
341
342 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
343 return state->Forbidden_instance_;
344 }
345
346 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x000000F0) == 0x00000090)) { 286 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x000000F0) == 0x00000090)) {
347 return decode_mult(insn, state); 287 return decode_mult(insn);
348 } 288 }
349 289
350 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000090)) { 290 // Catch any attempt to fall through...
351 return decode_sync(insn, state); 291 fprintf(stderr, "TABLE IS INCOMPLETE: dp_misc could not parse %08X",
352 } 292 insn.bits(31,0));
353 293 return Forbidden_instance_;
354 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01000000) && (true)) { 294 }
355 return state->DataProc_instance_; 295
356 }
357
358 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01200000) && (true)) {
359 return decode_msr_and_hints(insn, state);
360 }
361
362 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01900000) != 0x01000000) && (true)) {
363 return decode_dp_immed(insn, state);
364 }
365
366 // Catch any attempt to fall through...
367 fprintf(stderr, "TABLE IS INCOMPLETE: dp_misc could not parse %08X",insn.bits( 31,0));
368 return state->Forbidden_instance_;
369 }
370 296
371 /* 297 /*
372 * Implementation of table dp_reg. 298 * Implementation of table dp_reg.
373 * Specified by: See Section A5.2.1. 299 * Specified by: ('See Section A5.2.1',)
374 */ 300 */
375 static inline const ClassDecoder &decode_dp_reg( 301 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_reg(
376 const Instruction insn, const NamedArm32DecoderState *state) { 302 const nacl_arm_dec::Instruction insn) const {
303 UNREFERENCED_PARAMETER(insn);
304 if (((insn & 0x01800000) == 0x01800000)) {
305 return DataProc_instance_;
306 }
307
308 if (((insn & 0x01000000) == 0x00000000)) {
309 return DataProc_instance_;
310 }
311
377 if (((insn & 0x01900000) == 0x01100000)) { 312 if (((insn & 0x01900000) == 0x01100000)) {
378 return state->Test_instance_; 313 return Test_instance_;
379 } 314 }
380 315
381 if (((insn & 0x01800000) == 0x01800000)) { 316 // Catch any attempt to fall through...
382 return state->DataProc_instance_; 317 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",
383 } 318 insn.bits(31,0));
384 319 return Forbidden_instance_;
385 if (((insn & 0x01000000) == 0x00000000)) { 320 }
386 return state->DataProc_instance_; 321
387 }
388
389 // Catch any attempt to fall through...
390 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",insn.bits(3 1,0));
391 return state->Forbidden_instance_;
392 }
393 322
394 /* 323 /*
395 * Implementation of table dp_reg_shifted. 324 * Implementation of table dp_reg_shifted.
396 * Specified by: See Section A5.2.2. 325 * Specified by: ('See Section A5.2.2',)
397 */ 326 */
398 static inline const ClassDecoder &decode_dp_reg_shifted( 327 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_reg_shifted(
399 const Instruction insn, const NamedArm32DecoderState *state) { 328 const nacl_arm_dec::Instruction insn) const {
329 UNREFERENCED_PARAMETER(insn);
330 if (((insn & 0x01900000) == 0x01100000)) {
331 return Binary3RegisterShiftedTest_instance_;
332 }
333
334 if (((insn & 0x01E00000) == 0x01E00000)) {
335 return Unary3RegisterShiftedOp_instance_;
336 }
337
338 if (((insn & 0x01E00000) == 0x00800000)) {
339 return Add_Rule_7_A1_P26Binary4RegisterShiftedOp_instance_;
340 }
341
400 if (((insn & 0x01E00000) == 0x01A00000)) { 342 if (((insn & 0x01E00000) == 0x01A00000)) {
401 return state->DataProc_instance_; 343 return DataProc_instance_;
402 } 344 }
403 345
404 if (((insn & 0x01E00000) == 0x01E00000)) { 346 if (((insn & 0x01C00000) == 0x00000000)) {
405 return state->Unary3RegisterShiftedOp_instance_; 347 return Binary4RegisterShiftedOp_instance_;
406 } 348 }
407 349
408 if (((insn & 0x01900000) == 0x01100000)) { 350 if (((insn & 0x01600000) == 0x00400000)) {
409 return state->Binary3RegisterShiftedTest_instance_; 351 return Binary4RegisterShiftedOp_instance_;
410 } 352 }
411 353
354 if (((insn & 0x01A00000) == 0x00A00000)) {
355 return Binary4RegisterShiftedOp_instance_;
356 }
357
412 if (((insn & 0x01A00000) == 0x01800000)) { 358 if (((insn & 0x01A00000) == 0x01800000)) {
413 return state->Binary4RegisterShiftedOp_instance_; 359 return Binary4RegisterShiftedOp_instance_;
414 } 360 }
415 361
416 if (((insn & 0x01000000) == 0x00000000)) { 362 if (((insn & 0x01E00000) == 0x00600000)) {
417 return state->Binary4RegisterShiftedOp_instance_; 363 return Rsb_Rule_144_A1_P288Binary4RegisterShiftedOp_instance_;
418 } 364 }
419 365
420 // Catch any attempt to fall through... 366 // Catch any attempt to fall through...
421 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg_shifted could not parse %08X",ins n.bits(31,0)); 367 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg_shifted could not parse %08X",
422 return state->Forbidden_instance_; 368 insn.bits(31,0));
423 } 369 return Forbidden_instance_;
424 370 }
425 /* 371
426 * Implementation of table dp_immed. 372
427 * Specified by: See Section A5.2.3. 373 /*
428 */ 374 * Implementation of table extra_load_store.
429 static inline const ClassDecoder &decode_dp_immed( 375 * Specified by: ('See Section A5.2.8',)
430 const Instruction insn, const NamedArm32DecoderState *state) { 376 */
431 if (((insn & 0x01F00000) == 0x01100000)) { 377 const NamedClassDecoder& NamedArm32DecoderState::decode_extra_load_store(
432 return state->TestImmediate_instance_; 378 const nacl_arm_dec::Instruction insn) const {
433 } 379 UNREFERENCED_PARAMETER(insn);
434 380 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00400000) ) {
435 if (((insn & 0x01F00000) == 0x01500000)) { 381 return LoadDoubleI_instance_;
436 return state->Test_instance_; 382 }
437 } 383
438 384 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00100000) ) {
439 if (((insn & 0x01B00000) == 0x01300000)) { 385 return LoadRegister_instance_;
440 return state->Test_instance_; 386 }
441 } 387
442 388 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00100000) ) {
443 if (((insn & 0x01E00000) == 0x01C00000)) { 389 return LoadRegister_instance_;
444 return state->ImmediateBic_instance_; 390 }
445 } 391
446 392 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00000000) ) {
447 if (((insn & 0x01E00000) == 0x01E00000)) { 393 return LoadDoubleR_instance_;
448 return state->DataProc_instance_; 394 }
449 } 395
450 396 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00400000) ) {
451 if (((insn & 0x01C00000) == 0x00000000)) { 397 return StoreImmediate_instance_;
452 return state->DataProc_instance_; 398 }
453 } 399
454 400 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00000000) ) {
455 if (((insn & 0x00C00000) == 0x00800000)) { 401 return StoreRegister_instance_;
456 return state->DataProc_instance_; 402 }
457 } 403
458 404 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00500000) ) {
459 if (((insn & 0x01400000) == 0x00400000)) { 405 return LoadImmediate_instance_;
460 return state->DataProc_instance_; 406 }
461 } 407
462 408 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00500000) ) {
463 // Catch any attempt to fall through... 409 return LoadImmediate_instance_;
464 fprintf(stderr, "TABLE IS INCOMPLETE: dp_immed could not parse %08X",insn.bits (31,0)); 410 }
465 return state->Forbidden_instance_; 411
466 } 412 // Catch any attempt to fall through...
413 fprintf(stderr, "TABLE IS INCOMPLETE: extra_load_store could not parse %08X",
414 insn.bits(31,0));
415 return Forbidden_instance_;
416 }
417
418
419 /*
420 * Implementation of table half_mult.
421 * Specified by: ('See Section A5.2.7',)
422 */
423 const NamedClassDecoder& NamedArm32DecoderState::decode_half_mult(
424 const nacl_arm_dec::Instruction insn) const {
425 UNREFERENCED_PARAMETER(insn);
426 if (((insn & 0x00600000) == 0x00400000)) {
427 return LongMultiply_instance_;
428 }
429
430 if (((insn & 0x00600000) == 0x00600000)) {
431 return Multiply_instance_;
432 }
433
434 if (((insn & 0x00400000) == 0x00000000)) {
435 return Multiply_instance_;
436 }
437
438 // Catch any attempt to fall through...
439 fprintf(stderr, "TABLE IS INCOMPLETE: half_mult could not parse %08X",
440 insn.bits(31,0));
441 return Forbidden_instance_;
442 }
443
444
445 /*
446 * Implementation of table load_store_word_byte.
447 * Specified by: ('See Section A5.3',)
448 */
449 const NamedClassDecoder& NamedArm32DecoderState::decode_load_store_word_byte(
450 const nacl_arm_dec::Instruction insn) const {
451 UNREFERENCED_PARAMETER(insn);
452 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00100000) && (true)) {
453 return LoadImmediate_instance_;
454 }
455
456 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00000000) && (true)) {
457 return StoreImmediate_instance_;
458 }
459
460 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000010) == 0x00000000)) {
461 return LoadRegister_instance_;
462 }
463
464 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && (true)) {
465 return Forbidden_instance_;
466 }
467
468 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x00000010) == 0x00000000)) {
469 return Forbidden_instance_;
470 }
471
472 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
473 return StoreRegister_instance_;
474 }
475
476 // Catch any attempt to fall through...
477 fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08 X",
478 insn.bits(31,0));
479 return Forbidden_instance_;
480 }
481
482
483 /*
484 * Implementation of table media.
485 * Specified by: ('See Section A5.4',)
486 */
487 const NamedClassDecoder& NamedArm32DecoderState::decode_media(
488 const nacl_arm_dec::Instruction insn) const {
489
490 if ((true) && (true)) {
491 return Undefined_instance_;
492 }
493
494 if (((insn & 0x01800000) == 0x00800000) && (true)) {
495 return decode_pack_sat_rev(insn);
496 }
497
498 if (((insn & 0x01800000) == 0x00000000) && (true)) {
499 return decode_parallel_add_sub(insn);
500 }
501
502 if (((insn & 0x01800000) == 0x01000000) && (true)) {
503 return decode_signed_mult(insn);
504 }
505
506 if (((insn & 0x01A00000) == 0x01A00000) && ((insn & 0x00000060) == 0x00000040) ) {
507 return DataProc_instance_;
508 }
509
510 if (((insn & 0x01E00000) == 0x01C00000) && ((insn & 0x00000060) == 0x00000000) ) {
511 return DataProc_instance_;
512 }
513
514 if (((insn & 0x01F00000) == 0x01F00000) && ((insn & 0x000000E0) == 0x000000E0) ) {
515 return Roadblock_instance_;
516 }
517
518 if (((insn & 0x01F00000) == 0x01800000) && ((insn & 0x000000E0) == 0x00000000) ) {
519 return Multiply_instance_;
520 }
521
522 // Catch any attempt to fall through...
523 fprintf(stderr, "TABLE IS INCOMPLETE: media could not parse %08X",
524 insn.bits(31,0));
525 return Forbidden_instance_;
526 }
527
528
529 /*
530 * Implementation of table misc.
531 * Specified by: ('See Section A5.2.12',)
532 */
533 const NamedClassDecoder& NamedArm32DecoderState::decode_misc(
534 const nacl_arm_dec::Instruction insn) const {
535
536 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00200000) && (true)) {
537 return BxBlx_instance_;
538 }
539
540 if ((true) && (true) && (true)) {
541 return Undefined_instance_;
542 }
543
544 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00600000) && (true)) {
545 return DataProc_instance_;
546 }
547
548 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00000000)) {
549 return MoveToStatusRegister_instance_;
550 }
551
552 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00200000) == 0x00000000) && (true)) {
553 return DataProc_instance_;
554 }
555
556 if (((insn & 0x00000070) == 0x00000050) && (true) && (true)) {
557 return decode_sat_add_sub(insn);
558 }
559
560 if (((insn & 0x00000070) == 0x00000030) && ((insn & 0x00600000) == 0x00200000) && (true)) {
561 return BxBlx_instance_;
562 }
563
564 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00010000)) {
565 return Forbidden_instance_;
566 }
567
568 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00020000) == 0x00020000)) {
569 return Forbidden_instance_;
570 }
571
572 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00600000) && (true)) {
573 return Forbidden_instance_;
574 }
575
576 if (((insn & 0x00000070) == 0x00000020) && ((insn & 0x00600000) == 0x00200000) && (true)) {
577 return Forbidden_instance_;
578 }
579
580 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00600000) && (true)) {
581 return Forbidden_instance_;
582 }
583
584 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00200000) && (true)) {
585 return Breakpoint_instance_;
586 }
587
588 // Catch any attempt to fall through...
589 fprintf(stderr, "TABLE IS INCOMPLETE: misc could not parse %08X",
590 insn.bits(31,0));
591 return Forbidden_instance_;
592 }
593
594
595 /*
596 * Implementation of table misc_hints_simd.
597 * Specified by: ('See Section A5.7.1',)
598 */
599 const NamedClassDecoder& NamedArm32DecoderState::decode_misc_hints_simd(
600 const nacl_arm_dec::Instruction insn) const {
601
602 if (((insn & 0x06000000) == 0x02000000) && (true) && (true)) {
603 return decode_simd_dp(insn);
604 }
605
606 if (((insn & 0x07700000) == 0x04500000) && (true) && (true)) {
607 return EffectiveNoOp_instance_;
608 }
609
610 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000050) && (true)) {
611 return EffectiveNoOp_instance_;
612 }
613
614 if (((insn & 0x07700000) == 0x06500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
615 return EffectiveNoOp_instance_;
616 }
617
618 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000D0) == 0x00000040) && (true)) {
619 return EffectiveNoOp_instance_;
620 }
621
622 if ((true) && (true) && (true)) {
623 return Undefined_instance_;
624 }
625
626 if (((insn & 0x07100000) == 0x04000000) && (true) && (true)) {
627 return decode_simd_load_store(insn);
628 }
629
630 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
631 return Unpredictable_instance_;
632 }
633
634 if (((insn & 0x06300000) == 0x04300000) && (true) && (true)) {
635 return Unpredictable_instance_;
636 }
637
638 if (((insn & 0x06300000) == 0x06300000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
639 return Unpredictable_instance_;
640 }
641
642 if (((insn & 0x07700000) == 0x07500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
643 return EffectiveNoOp_instance_;
644 }
645
646 if (((insn & 0x07700000) == 0x05500000) && (true) && (true)) {
647 return EffectiveNoOp_instance_;
648 }
649
650 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000010) && (true)) {
651 return EffectiveNoOp_instance_;
652 }
653
654 if (((insn & 0x07700000) == 0x04100000) && (true) && (true)) {
655 return EffectiveNoOp_instance_;
656 }
657
658 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
659 return EffectiveNoOp_instance_;
660 }
661
662 if (((insn & 0x06700000) == 0x06100000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
663 return EffectiveNoOp_instance_;
664 }
665
666 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x00000020) == 0x00000000) && ((insn & 0x00010000) == 0x00000000)) {
667 return Forbidden_instance_;
668 }
669
670 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000000) && ((insn & 0x00010000) == 0x00010000)) {
671 return Forbidden_instance_;
672 }
673
674 // Catch any attempt to fall through...
675 fprintf(stderr, "TABLE IS INCOMPLETE: misc_hints_simd could not parse %08X",
676 insn.bits(31,0));
677 return Forbidden_instance_;
678 }
679
680
681 /*
682 * Implementation of table msr_and_hints.
683 * Specified by: ('See Section A5.2.11',)
684 */
685 const NamedClassDecoder& NamedArm32DecoderState::decode_msr_and_hints(
686 const nacl_arm_dec::Instruction insn) const {
687 UNREFERENCED_PARAMETER(insn);
688 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000002)) {
689 return EffectiveNoOp_instance_;
690 }
691
692 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000004)) {
693 return EffectiveNoOp_instance_;
694 }
695
696 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FD) == 0x00000001)) {
697 return EffectiveNoOp_instance_;
698 }
699
700 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000000)) {
701 return EffectiveNoOp_instance_;
702 }
703
704 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00030000) == 0x00010000) && (true)) {
705 return Forbidden_instance_;
706 }
707
708 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00020000) == 0x00020000) && (true)) {
709 return Forbidden_instance_;
710 }
711
712 if (((insn & 0x00400000) == 0x00400000) && (true) && (true)) {
713 return Forbidden_instance_;
714 }
715
716 if ((true) && (true) && (true)) {
717 return Forbidden_instance_;
718 }
719
720 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000F0) == 0x000000F0)) {
721 return EffectiveNoOp_instance_;
722 }
723
724 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00040000) && (true)) {
725 return MoveToStatusRegister_instance_;
726 }
727
728 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000B0000) == 0x00080000) && (true)) {
729 return MoveToStatusRegister_instance_;
730 }
731
732 // Catch any attempt to fall through...
733 fprintf(stderr, "TABLE IS INCOMPLETE: msr_and_hints could not parse %08X",
734 insn.bits(31,0));
735 return Forbidden_instance_;
736 }
737
467 738
468 /* 739 /*
469 * Implementation of table mult. 740 * Implementation of table mult.
470 * Specified by: See Section A5.2.5. 741 * Specified by: ('See Section A5.2.5',)
471 */ 742 */
472 static inline const ClassDecoder &decode_mult( 743 const NamedClassDecoder& NamedArm32DecoderState::decode_mult(
473 const Instruction insn, const NamedArm32DecoderState *state) { 744 const nacl_arm_dec::Instruction insn) const {
745 UNREFERENCED_PARAMETER(insn);
746 if (((insn & 0x00C00000) == 0x00000000)) {
747 return Multiply_instance_;
748 }
749
750 if (((insn & 0x00800000) == 0x00800000)) {
751 return LongMultiply_instance_;
752 }
753
754 if (((insn & 0x00D00000) == 0x00500000)) {
755 return Undefined_instance_;
756 }
757
474 if (((insn & 0x00F00000) == 0x00400000)) { 758 if (((insn & 0x00F00000) == 0x00400000)) {
475 return state->LongMultiply_instance_; 759 return LongMultiply_instance_;
476 } 760 }
477 761
478 if (((insn & 0x00F00000) == 0x00600000)) { 762 if (((insn & 0x00F00000) == 0x00600000)) {
479 return state->Multiply_instance_; 763 return Multiply_instance_;
480 } 764 }
481 765
482 if (((insn & 0x00D00000) == 0x00500000)) { 766 // Catch any attempt to fall through...
483 return state->Undefined_instance_; 767 fprintf(stderr, "TABLE IS INCOMPLETE: mult could not parse %08X",
484 } 768 insn.bits(31,0));
485 769 return Forbidden_instance_;
486 if (((insn & 0x00C00000) == 0x00000000)) { 770 }
487 return state->Multiply_instance_; 771
488 } 772
489 773 /*
490 if (((insn & 0x00800000) == 0x00800000)) { 774 * Implementation of table pack_sat_rev.
491 return state->LongMultiply_instance_; 775 * Specified by: ('See Section A5.4.3',)
492 } 776 */
493 777 const NamedClassDecoder& NamedArm32DecoderState::decode_pack_sat_rev(
494 // Catch any attempt to fall through... 778 const nacl_arm_dec::Instruction insn) const {
495 fprintf(stderr, "TABLE IS INCOMPLETE: mult could not parse %08X",insn.bits(31, 0)); 779 UNREFERENCED_PARAMETER(insn);
496 return state->Forbidden_instance_; 780 if (((insn & 0x00700000) == 0x00700000) && ((insn & 0x000000E0) == 0x00000020) ) {
497 } 781 return PackSatRev_instance_;
782 }
783
784 if ((true) && (true)) {
785 return Undefined_instance_;
786 }
787
788 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000020) == 0x00000000) ) {
789 return PackSatRev_instance_;
790 }
791
792 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000E0) == 0x000000A0) ) {
793 return PackSatRev_instance_;
794 }
795
796 if (((insn & 0x00200000) == 0x00200000) && ((insn & 0x00000020) == 0x00000000) ) {
797 return PackSatRev_instance_;
798 }
799
800 if (((insn & 0x00600000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000020) ) {
801 return PackSatRev_instance_;
802 }
803
804 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x000000A0) ) {
805 return PackSatRev_instance_;
806 }
807
808 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x000000E0) == 0x00000060) ) {
809 return PackSatRev_instance_;
810 }
811
812 if (((insn & 0x00700000) == 0x00600000) && ((insn & 0x000000A0) == 0x00000020) ) {
813 return PackSatRev_instance_;
814 }
815
816 if (((insn & 0x00500000) == 0x00000000) && ((insn & 0x000000E0) == 0x00000060) ) {
817 return PackSatRev_instance_;
818 }
819
820 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x00000060) ) {
821 return PackSatRev_instance_;
822 }
823
824 // Catch any attempt to fall through...
825 fprintf(stderr, "TABLE IS INCOMPLETE: pack_sat_rev could not parse %08X",
826 insn.bits(31,0));
827 return Forbidden_instance_;
828 }
829
830
831 /*
832 * Implementation of table parallel_add_sub.
833 * Specified by: ('See Sections A5.4.1, A5.4.2',)
834 */
835 const NamedClassDecoder& NamedArm32DecoderState::decode_parallel_add_sub(
836 const nacl_arm_dec::Instruction insn) const {
837 UNREFERENCED_PARAMETER(insn);
838 if ((true) && (true)) {
839 return Undefined_instance_;
840 }
841
842 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000080) ) {
843 return DataProc_instance_;
844 }
845
846 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x000000E0) ) {
847 return DataProc_instance_;
848 }
849
850 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x00000080) ) {
851 return DataProc_instance_;
852 }
853
854 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x000000E0) ) {
855 return DataProc_instance_;
856 }
857
858 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x00000080) == 0x00000000) ) {
859 return DataProc_instance_;
860 }
861
862 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000080) == 0x00000000) ) {
863 return DataProc_instance_;
864 }
865
866 // Catch any attempt to fall through...
867 fprintf(stderr, "TABLE IS INCOMPLETE: parallel_add_sub could not parse %08X",
868 insn.bits(31,0));
869 return Forbidden_instance_;
870 }
871
498 872
499 /* 873 /*
500 * Implementation of table sat_add_sub. 874 * Implementation of table sat_add_sub.
501 * Specified by: See Section A5.2.6. 875 * Specified by: ('See Section A5.2.6',)
502 */ 876 */
503 static inline const ClassDecoder &decode_sat_add_sub( 877 const NamedClassDecoder& NamedArm32DecoderState::decode_sat_add_sub(
504 const Instruction insn, const NamedArm32DecoderState *state) { 878 const nacl_arm_dec::Instruction insn) const {
879 UNREFERENCED_PARAMETER(insn);
505 if ((true)) { 880 if ((true)) {
506 return state->SatAddSub_instance_; 881 return SatAddSub_instance_;
507 } 882 }
508 883
509 // Catch any attempt to fall through... 884 // Catch any attempt to fall through...
510 fprintf(stderr, "TABLE IS INCOMPLETE: sat_add_sub could not parse %08X",insn.b its(31,0)); 885 fprintf(stderr, "TABLE IS INCOMPLETE: sat_add_sub could not parse %08X",
511 return state->Forbidden_instance_; 886 insn.bits(31,0));
512 } 887 return Forbidden_instance_;
513 888 }
514 /* 889
515 * Implementation of table half_mult. 890
516 * Specified by: See Section A5.2.7. 891 /*
517 */ 892 * Implementation of table signed_mult.
518 static inline const ClassDecoder &decode_half_mult( 893 * Specified by: ('See Section A5.4.4',)
519 const Instruction insn, const NamedArm32DecoderState *state) { 894 */
520 if (((insn & 0x00600000) == 0x00400000)) { 895 const NamedClassDecoder& NamedArm32DecoderState::decode_signed_mult(
521 return state->LongMultiply_instance_; 896 const nacl_arm_dec::Instruction insn) const {
522 } 897 UNREFERENCED_PARAMETER(insn);
523 898 if ((true) && (true) && (true)) {
524 if (((insn & 0x00600000) == 0x00600000)) { 899 return Undefined_instance_;
525 return state->Multiply_instance_; 900 }
526 } 901
527 902 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
528 if (((insn & 0x00400000) == 0x00000000)) { 903 return LongMultiply_instance_;
529 return state->Multiply_instance_; 904 }
530 } 905
531 906 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000C0) == 0x00000040) && ((insn & 0x0000F000) != 0x0000F000)) {
532 // Catch any attempt to fall through... 907 return Multiply_instance_;
533 fprintf(stderr, "TABLE IS INCOMPLETE: half_mult could not parse %08X",insn.bit s(31,0)); 908 }
534 return state->Forbidden_instance_; 909
535 } 910 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x000000C0) && (true)) {
536 911 return Multiply_instance_;
537 /* 912 }
538 * Implementation of table extra_load_store. 913
539 * Specified by: See Section A5.2.8. 914 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
540 */ 915 return Multiply_instance_;
541 static inline const ClassDecoder &decode_extra_load_store( 916 }
542 const Instruction insn, const NamedArm32DecoderState *state) { 917
543 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00000000) ) { 918 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x00000000) && (true)) {
544 return state->LoadDoubleR_instance_; 919 return Multiply_instance_;
545 } 920 }
546 921
547 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00100000) ) { 922 // Catch any attempt to fall through...
548 return state->LoadRegister_instance_; 923 fprintf(stderr, "TABLE IS INCOMPLETE: signed_mult could not parse %08X",
549 } 924 insn.bits(31,0));
550 925 return Forbidden_instance_;
551 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00400000) ) { 926 }
552 return state->LoadDoubleI_instance_; 927
553 } 928
554 929 /*
555 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00500000) ) { 930 * Implementation of table simd_dp.
556 return state->LoadImmediate_instance_; 931 * Specified by: ('See Section A7.4',)
557 } 932 */
558 933 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp(
559 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00000000) ) { 934 const nacl_arm_dec::Instruction insn) const {
560 return state->StoreRegister_instance_; 935
561 } 936 if ((true) && (true) && (true) && (true)) {
562 937 return Undefined_instance_;
563 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00100000) ) { 938 }
564 return state->LoadRegister_instance_; 939
565 } 940 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
566 941 return decode_simd_dp_3diff(insn);
567 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00400000) ) { 942 }
568 return state->StoreImmediate_instance_; 943
569 } 944 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
570 945 return decode_simd_dp_3diff(insn);
571 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00500000) ) { 946 }
572 return state->LoadImmediate_instance_; 947
573 } 948 if ((true) && ((insn & 0x00800000) == 0x00000000) && (true) && (true)) {
574 949 return decode_simd_dp_3same(insn);
575 // Catch any attempt to fall through... 950 }
576 fprintf(stderr, "TABLE IS INCOMPLETE: extra_load_store could not parse %08X",i nsn.bits(31,0)); 951
577 return state->Forbidden_instance_; 952 if ((true) && ((insn & 0x00B80000) == 0x00880000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
578 } 953 return decode_simd_dp_2shift(insn);
954 }
955
956 if ((true) && ((insn & 0x00B00000) == 0x00900000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
957 return decode_simd_dp_2shift(insn);
958 }
959
960 if ((true) && ((insn & 0x00A00000) == 0x00A00000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
961 return decode_simd_dp_2shift(insn);
962 }
963
964 if ((true) && ((insn & 0x00800000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000090)) {
965 return decode_simd_dp_2shift(insn);
966 }
967
968 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
969 return decode_simd_dp_2scalar(insn);
970 }
971
972 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
973 return decode_simd_dp_2scalar(insn);
974 }
975
976 if ((true) && ((insn & 0x00B80000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
977 return decode_simd_dp_1imm(insn);
978 }
979
980 if (((insn & 0x01000000) == 0x00000000) && ((insn & 0x00B00000) == 0x00B00000) && (true) && ((insn & 0x00000010) == 0x00000000)) {
981 return EffectiveNoOp_instance_;
982 }
983
984 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000C00) == 0x00000800) && ((insn & 0x00000010) == 0x00000000)) {
985 return EffectiveNoOp_instance_;
986 }
987
988 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000F00) == 0x00000C00) && ((insn & 0x00000090) == 0x00000000)) {
989 return EffectiveNoOp_instance_;
990 }
991
992 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000800) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
993 return decode_simd_dp_2misc(insn);
994 }
995
996 // Catch any attempt to fall through...
997 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp could not parse %08X",
998 insn.bits(31,0));
999 return Forbidden_instance_;
1000 }
1001
1002
1003 /*
1004 * Implementation of table simd_dp_1imm.
1005 * Specified by: ('See Section A7.4.6',)
1006 */
1007 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_1imm(
1008 const nacl_arm_dec::Instruction insn) const {
1009 UNREFERENCED_PARAMETER(insn);
1010 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000F00) ) {
1011 return Undefined_instance_;
1012 }
1013
1014 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000E00) == 0x00000C00) ) {
1015 return EffectiveNoOp_instance_;
1016 }
1017
1018 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000E00) ) {
1019 return EffectiveNoOp_instance_;
1020 }
1021
1022 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000800) == 0x00000000) ) {
1023 return EffectiveNoOp_instance_;
1024 }
1025
1026 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000C00) == 0x00000800) ) {
1027 return EffectiveNoOp_instance_;
1028 }
1029
1030 if (((insn & 0x00000020) == 0x00000000) && (true)) {
1031 return EffectiveNoOp_instance_;
1032 }
1033
1034 // Catch any attempt to fall through...
1035 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_1imm could not parse %08X",
1036 insn.bits(31,0));
1037 return Forbidden_instance_;
1038 }
1039
1040
1041 /*
1042 * Implementation of table simd_dp_2misc.
1043 * Specified by: ('See Section A7.4.5',)
1044 */
1045 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_2misc(
1046 const nacl_arm_dec::Instruction insn) const {
1047 UNREFERENCED_PARAMETER(insn);
1048 if ((true) && (true)) {
1049 return Undefined_instance_;
1050 }
1051
1052 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000780) == 0x00000700) ) {
1053 return EffectiveNoOp_instance_;
1054 }
1055
1056 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000380) == 0x00000380) ) {
1057 return EffectiveNoOp_instance_;
1058 }
1059
1060 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000007C0) == 0x00000300) ) {
1061 return EffectiveNoOp_instance_;
1062 }
1063
1064 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000006C0) == 0x00000600) ) {
1065 return EffectiveNoOp_instance_;
1066 }
1067
1068 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000380) == 0x00000100) ) {
1069 return EffectiveNoOp_instance_;
1070 }
1071
1072 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000580) == 0x00000580) ) {
1073 return EffectiveNoOp_instance_;
1074 }
1075
1076 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000280) == 0x00000200) ) {
1077 return EffectiveNoOp_instance_;
1078 }
1079
1080 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000700) == 0x00000200) ) {
1081 return EffectiveNoOp_instance_;
1082 }
1083
1084 if (((insn & 0x00030000) == 0x00030000) && ((insn & 0x00000400) == 0x00000400) ) {
1085 return EffectiveNoOp_instance_;
1086 }
1087
1088 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000100) == 0x00000000) ) {
1089 return EffectiveNoOp_instance_;
1090 }
1091
1092 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000200) == 0x00000000) ) {
1093 return EffectiveNoOp_instance_;
1094 }
1095
1096 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000600) == 0x00000000) ) {
1097 return EffectiveNoOp_instance_;
1098 }
1099
1100 // Catch any attempt to fall through...
1101 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2misc could not parse %08X",
1102 insn.bits(31,0));
1103 return Forbidden_instance_;
1104 }
1105
1106
1107 /*
1108 * Implementation of table simd_dp_2scalar.
1109 * Specified by: ('See Section A7.4.3',)
1110 */
1111 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_2scalar(
1112 const nacl_arm_dec::Instruction insn) const {
1113 UNREFERENCED_PARAMETER(insn);
1114 if ((true) && (true)) {
1115 return Undefined_instance_;
1116 }
1117
1118 if (((insn & 0x00000B00) == 0x00000200) && (true)) {
1119 return EffectiveNoOp_instance_;
1120 }
1121
1122 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x01000000) == 0x00000000) ) {
1123 return EffectiveNoOp_instance_;
1124 }
1125
1126 if (((insn & 0x00000F00) == 0x00000A00) && (true)) {
1127 return EffectiveNoOp_instance_;
1128 }
1129
1130 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x01000000) == 0x00000000) ) {
1131 return EffectiveNoOp_instance_;
1132 }
1133
1134 if (((insn & 0x00000200) == 0x00000000) && (true)) {
1135 return EffectiveNoOp_instance_;
1136 }
1137
1138 // Catch any attempt to fall through...
1139 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2scalar could not parse %08X",
1140 insn.bits(31,0));
1141 return Forbidden_instance_;
1142 }
1143
1144
1145 /*
1146 * Implementation of table simd_dp_2shift.
1147 * Specified by: ('See Section A7.4.4',)
1148 */
1149 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_2shift(
1150 const nacl_arm_dec::Instruction insn) const {
1151 UNREFERENCED_PARAMETER(insn);
1152 if ((true) && (true) && (true) && (true)) {
1153 return Undefined_instance_;
1154 }
1155
1156 if (((insn & 0x00000F00) == 0x00000500) && ((insn & 0x01000000) == 0x00000000) && (true) && (true)) {
1157 return EffectiveNoOp_instance_;
1158 }
1159
1160 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x00000040) == 0x00000000) && ((insn & 0x00000080) == 0x00000000)) {
1161 return EffectiveNoOp_instance_;
1162 }
1163
1164 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00000040) == 0x00000000) && (true)) {
1165 return EffectiveNoOp_instance_;
1166 }
1167
1168 if (((insn & 0x00000F00) == 0x00000A00) && (true) && ((insn & 0x00000040) == 0 x00000000) && (true)) {
1169 return EffectiveNoOp_instance_;
1170 }
1171
1172 if (((insn & 0x00000E00) == 0x00000400) && ((insn & 0x01000000) == 0x01000000) && (true) && (true)) {
1173 return EffectiveNoOp_instance_;
1174 }
1175
1176 if (((insn & 0x00000600) == 0x00000600) && (true) && (true) && (true)) {
1177 return EffectiveNoOp_instance_;
1178 }
1179
1180 if (((insn & 0x00000F00) == 0x00000800) && (true) && ((insn & 0x00000040) == 0 x00000040) && (true)) {
1181 return EffectiveNoOp_instance_;
1182 }
1183
1184 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1185 return EffectiveNoOp_instance_;
1186 }
1187
1188 if (((insn & 0x00000C00) == 0x00000000) && (true) && (true) && (true)) {
1189 return EffectiveNoOp_instance_;
1190 }
1191
1192 // Catch any attempt to fall through...
1193 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2shift could not parse %08X",
1194 insn.bits(31,0));
1195 return Forbidden_instance_;
1196 }
1197
1198
1199 /*
1200 * Implementation of table simd_dp_3diff.
1201 * Specified by: ('See Section A7.4.2',)
1202 */
1203 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_3diff(
1204 const nacl_arm_dec::Instruction insn) const {
1205 UNREFERENCED_PARAMETER(insn);
1206 if ((true) && (true)) {
1207 return Undefined_instance_;
1208 }
1209
1210 if (((insn & 0x00000D00) == 0x00000900) && ((insn & 0x01000000) == 0x00000000) ) {
1211 return EffectiveNoOp_instance_;
1212 }
1213
1214 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x01000000) == 0x00000000) ) {
1215 return EffectiveNoOp_instance_;
1216 }
1217
1218 if (((insn & 0x00000900) == 0x00000800) && (true)) {
1219 return EffectiveNoOp_instance_;
1220 }
1221
1222 if (((insn & 0x00000800) == 0x00000000) && (true)) {
1223 return EffectiveNoOp_instance_;
1224 }
1225
1226 // Catch any attempt to fall through...
1227 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3diff could not parse %08X",
1228 insn.bits(31,0));
1229 return Forbidden_instance_;
1230 }
1231
1232
1233 /*
1234 * Implementation of table simd_dp_3same.
1235 * Specified by: ('See Section A7.4.1',)
1236 */
1237 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_3same(
1238 const nacl_arm_dec::Instruction insn) const {
1239 UNREFERENCED_PARAMETER(insn);
1240 if ((true) && (true) && (true) && (true)) {
1241 return Undefined_instance_;
1242 }
1243
1244 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00000000)) {
1245 return EffectiveNoOp_instance_;
1246 }
1247
1248 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00200000)) {
1249 return EffectiveNoOp_instance_;
1250 }
1251
1252 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1253 return EffectiveNoOp_instance_;
1254 }
1255
1256 if (((insn & 0x00000D00) == 0x00000100) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1257 return EffectiveNoOp_instance_;
1258 }
1259
1260 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1261 return EffectiveNoOp_instance_;
1262 }
1263
1264 if (((insn & 0x00000F00) == 0x00000500) && (true) && (true) && (true)) {
1265 return EffectiveNoOp_instance_;
1266 }
1267
1268 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1269 return EffectiveNoOp_instance_;
1270 }
1271
1272 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1273 return EffectiveNoOp_instance_;
1274 }
1275
1276 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1277 return EffectiveNoOp_instance_;
1278 }
1279
1280 if (((insn & 0x00000F00) == 0x00000D00) && (true) && ((insn & 0x01000000) == 0 x00000000) && (true)) {
1281 return EffectiveNoOp_instance_;
1282 }
1283
1284 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && (true) && ((insn & 0x00200000) == 0x00000000)) {
1285 return EffectiveNoOp_instance_;
1286 }
1287
1288 if (((insn & 0x00000700) == 0x00000700) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1289 return EffectiveNoOp_instance_;
1290 }
1291
1292 if (((insn & 0x00000B00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x00000000) && (true)) {
1293 return EffectiveNoOp_instance_;
1294 }
1295
1296 if (((insn & 0x00000900) == 0x00000000) && (true) && (true) && (true)) {
1297 return EffectiveNoOp_instance_;
1298 }
1299
1300 if (((insn & 0x00000D00) == 0x00000800) && (true) && (true) && (true)) {
1301 return EffectiveNoOp_instance_;
1302 }
1303
1304 if (((insn & 0x00000F00) == 0x00000100) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1305 return EffectiveNoOp_instance_;
1306 }
1307
1308 // Catch any attempt to fall through...
1309 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3same could not parse %08X",
1310 insn.bits(31,0));
1311 return Forbidden_instance_;
1312 }
1313
1314
1315 /*
1316 * Implementation of table simd_load_store.
1317 * Specified by: ('See Section A7.7',)
1318 */
1319 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_load_store(
1320 const nacl_arm_dec::Instruction insn) const {
1321
1322 if (((insn & 0x00200000) == 0x00000000)) {
1323 return decode_simd_load_store_l0(insn);
1324 }
1325
1326 if (((insn & 0x00200000) == 0x00200000)) {
1327 return decode_simd_load_store_l1(insn);
1328 }
1329
1330 // Catch any attempt to fall through...
1331 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store could not parse %08X",
1332 insn.bits(31,0));
1333 return Forbidden_instance_;
1334 }
1335
1336
1337 /*
1338 * Implementation of table simd_load_store_l0.
1339 * Specified by: ('See Section A7.7, Table A7 - 20',)
1340 */
1341 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_load_store_l0(
1342 const nacl_arm_dec::Instruction insn) const {
1343 UNREFERENCED_PARAMETER(insn);
1344 if ((true) && (true)) {
1345 return Undefined_instance_;
1346 }
1347
1348 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1349 return VectorStore_instance_;
1350 }
1351
1352 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1353 return VectorStore_instance_;
1354 }
1355
1356 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1357 return VectorStore_instance_;
1358 }
1359
1360 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1361 return VectorStore_instance_;
1362 }
1363
1364 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000800) == 0x00000000) ) {
1365 return VectorStore_instance_;
1366 }
1367
1368 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000C00) == 0x00000800) ) {
1369 return VectorStore_instance_;
1370 }
1371
1372 // Catch any attempt to fall through...
1373 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l0 could not parse %08X" ,
1374 insn.bits(31,0));
1375 return Forbidden_instance_;
1376 }
1377
1378
1379 /*
1380 * Implementation of table simd_load_store_l1.
1381 * Specified by: ('See Section A7.7, Table A7 - 21',)
1382 */
1383 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_load_store_l1(
1384 const nacl_arm_dec::Instruction insn) const {
1385 UNREFERENCED_PARAMETER(insn);
1386 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1387 return VectorLoad_instance_;
1388 }
1389
1390 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1391 return VectorLoad_instance_;
1392 }
1393
1394 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1395 return VectorLoad_instance_;
1396 }
1397
1398 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1399 return VectorLoad_instance_;
1400 }
1401
1402 if (((insn & 0x00800000) == 0x00800000) && (true)) {
1403 return VectorLoad_instance_;
1404 }
1405
1406 if ((true) && (true)) {
1407 return Undefined_instance_;
1408 }
1409
1410 // Catch any attempt to fall through...
1411 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l1 could not parse %08X" ,
1412 insn.bits(31,0));
1413 return Forbidden_instance_;
1414 }
1415
1416
1417 /*
1418 * Implementation of table super_cop.
1419 * Specified by: ('See Section A5.6',)
1420 */
1421 const NamedClassDecoder& NamedArm32DecoderState::decode_super_cop(
1422 const nacl_arm_dec::Instruction insn) const {
1423 UNREFERENCED_PARAMETER(insn);
1424 if (((insn & 0x03100000) == 0x02100000) && ((insn & 0x00000010) == 0x00000010) ) {
1425 return MoveFromCoprocessor_instance_;
1426 }
1427
1428 if (((insn & 0x02100000) == 0x00000000) && (true)) {
1429 return StoreCoprocessor_instance_;
1430 }
1431
1432 if (((insn & 0x03F00000) == 0x00400000) && (true)) {
1433 return CoprocessorOp_instance_;
1434 }
1435
1436 if (((insn & 0x03E00000) == 0x00000000) && (true)) {
1437 return Undefined_instance_;
1438 }
1439
1440 if (((insn & 0x02100000) == 0x00100000) && (true)) {
1441 return LoadCoprocessor_instance_;
1442 }
1443
1444 if (((insn & 0x03000000) == 0x02000000) && ((insn & 0x00000010) == 0x00000000) ) {
1445 return CoprocessorOp_instance_;
1446 }
1447
1448 if (((insn & 0x03100000) == 0x02000000) && ((insn & 0x00000010) == 0x00000010) ) {
1449 return CoprocessorOp_instance_;
1450 }
1451
1452 if (((insn & 0x03F00000) == 0x00500000) && (true)) {
1453 return MoveDoubleFromCoprocessor_instance_;
1454 }
1455
1456 if (((insn & 0x03000000) == 0x03000000) && (true)) {
1457 return Forbidden_instance_;
1458 }
1459
1460 // Catch any attempt to fall through...
1461 fprintf(stderr, "TABLE IS INCOMPLETE: super_cop could not parse %08X",
1462 insn.bits(31,0));
1463 return Forbidden_instance_;
1464 }
1465
579 1466
580 /* 1467 /*
581 * Implementation of table sync. 1468 * Implementation of table sync.
582 * Specified by: See Section A5.2.10. 1469 * Specified by: ('See Section A5.2.10',)
583 */ 1470 */
584 static inline const ClassDecoder &decode_sync( 1471 const NamedClassDecoder& NamedArm32DecoderState::decode_sync(
585 const Instruction insn, const NamedArm32DecoderState *state) { 1472 const nacl_arm_dec::Instruction insn) const {
1473 UNREFERENCED_PARAMETER(insn);
1474 if (((insn & 0x00B00000) == 0x00000000)) {
1475 return Deprecated_instance_;
1476 }
1477
1478 if (((insn & 0x00F00000) == 0x00B00000)) {
1479 return LoadDoubleExclusive_instance_;
1480 }
1481
1482 if ((true)) {
1483 return Undefined_instance_;
1484 }
1485
1486 if (((insn & 0x00F00000) == 0x00C00000)) {
1487 return StoreExclusive_instance_;
1488 }
1489
1490 if (((insn & 0x00B00000) == 0x00A00000)) {
1491 return StoreExclusive_instance_;
1492 }
1493
1494 if (((insn & 0x00F00000) == 0x00900000)) {
1495 return LoadExclusive_instance_;
1496 }
1497
586 if (((insn & 0x00F00000) == 0x00800000)) { 1498 if (((insn & 0x00F00000) == 0x00800000)) {
587 return state->StoreExclusive_instance_; 1499 return StoreExclusive_instance_;
588 } 1500 }
589 1501
590 if (((insn & 0x00F00000) == 0x00900000)) {
591 return state->LoadExclusive_instance_;
592 }
593
594 if (((insn & 0x00F00000) == 0x00B00000)) {
595 return state->LoadDoubleExclusive_instance_;
596 }
597
598 if (((insn & 0x00F00000) == 0x00C00000)) {
599 return state->StoreExclusive_instance_;
600 }
601
602 if (((insn & 0x00B00000) == 0x00000000)) {
603 return state->Deprecated_instance_;
604 }
605
606 if (((insn & 0x00B00000) == 0x00A00000)) {
607 return state->StoreExclusive_instance_;
608 }
609
610 if (((insn & 0x00D00000) == 0x00D00000)) { 1502 if (((insn & 0x00D00000) == 0x00D00000)) {
611 return state->LoadExclusive_instance_; 1503 return LoadExclusive_instance_;
612 } 1504 }
613 1505
614 if ((true)) { 1506 // Catch any attempt to fall through...
615 return state->Undefined_instance_; 1507 fprintf(stderr, "TABLE IS INCOMPLETE: sync could not parse %08X",
616 } 1508 insn.bits(31,0));
617 1509 return Forbidden_instance_;
618 // Catch any attempt to fall through... 1510 }
619 fprintf(stderr, "TABLE IS INCOMPLETE: sync could not parse %08X",insn.bits(31, 0)); 1511
620 return state->Forbidden_instance_; 1512
621 } 1513 /*
622 1514 * Implementation of table unconditional.
623 /* 1515 * Specified by: ('See Section A5.7',)
624 * Implementation of table msr_and_hints. 1516 */
625 * Specified by: See Section A5.2.11. 1517 const NamedClassDecoder& NamedArm32DecoderState::decode_unconditional(
626 */ 1518 const nacl_arm_dec::Instruction insn) const {
627 static inline const ClassDecoder &decode_msr_and_hints( 1519
628 const Instruction insn, const NamedArm32DecoderState *state) { 1520 if (((insn & 0x08000000) == 0x00000000) && (true) && (true)) {
629 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000000)) { 1521 return decode_misc_hints_simd(insn);
630 return state->EffectiveNoOp_instance_; 1522 }
631 } 1523
632 1524 if (((insn & 0x0F100000) == 0x0E100000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
633 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000002)) { 1525 return MoveFromCoprocessor_instance_;
634 return state->EffectiveNoOp_instance_; 1526 }
635 } 1527
636 1528 if (((insn & 0x0FB00000) == 0x0C300000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
637 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000004)) { 1529 return LoadCoprocessor_instance_;
638 return state->EffectiveNoOp_instance_; 1530 }
639 } 1531
640 1532 if (((insn & 0x0F900000) == 0x0C900000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
641 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FD) == 0x00000001)) { 1533 return LoadCoprocessor_instance_;
642 return state->EffectiveNoOp_instance_; 1534 }
643 } 1535
644 1536 if (((insn & 0x0F100000) == 0x0D100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
645 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000F0) == 0x000000F0)) { 1537 return LoadCoprocessor_instance_;
646 return state->EffectiveNoOp_instance_; 1538 }
647 } 1539
648
649 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00040000) && (true)) {
650 return state->MoveToStatusRegister_instance_;
651 }
652
653 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000B0000) == 0x00080000) && (true)) {
654 return state->MoveToStatusRegister_instance_;
655 }
656
657 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00030000) == 0x00010000) && (true)) {
658 return state->Forbidden_instance_;
659 }
660
661 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00020000) == 0x00020000) && (true)) {
662 return state->Forbidden_instance_;
663 }
664
665 if (((insn & 0x00400000) == 0x00400000) && (true) && (true)) {
666 return state->Forbidden_instance_;
667 }
668
669 if ((true) && (true) && (true)) { 1540 if ((true) && (true) && (true)) {
670 return state->Forbidden_instance_; 1541 return Undefined_instance_;
671 } 1542 }
672 1543
673 // Catch any attempt to fall through... 1544 if (((insn & 0x0FF00000) == 0x0C500000) && (true) && (true)) {
674 fprintf(stderr, "TABLE IS INCOMPLETE: msr_and_hints could not parse %08X",insn .bits(31,0)); 1545 return MoveDoubleFromCoprocessor_instance_;
675 return state->Forbidden_instance_; 1546 }
676 } 1547
677 1548 if (((insn & 0x0F000000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
678 /* 1549 return CoprocessorOp_instance_;
679 * Implementation of table misc. 1550 }
680 * Specified by: See Section A5.2.12. 1551
681 */ 1552 if (((insn & 0x0F100000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
682 static inline const ClassDecoder &decode_misc( 1553 return CoprocessorOp_instance_;
683 const Instruction insn, const NamedArm32DecoderState *state) { 1554 }
684 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00000000)) { 1555
685 return state->MoveToStatusRegister_instance_; 1556 if (((insn & 0x0FB00000) == 0x0C200000) && (true) && (true)) {
686 } 1557 return StoreCoprocessor_instance_;
687 1558 }
688 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00010000)) { 1559
689 return state->Forbidden_instance_; 1560 if (((insn & 0x0F900000) == 0x0C800000) && (true) && (true)) {
690 } 1561 return StoreCoprocessor_instance_;
691 1562 }
692 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00020000) == 0x00020000)) { 1563
693 return state->Forbidden_instance_; 1564 if (((insn & 0x0F100000) == 0x0D000000) && (true) && (true)) {
694 } 1565 return StoreCoprocessor_instance_;
695 1566 }
696 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00600000) && (true)) { 1567
697 return state->Forbidden_instance_;
698 }
699
700 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00200000) == 0x00000000) && (true)) {
701 return state->DataProc_instance_;
702 }
703
704 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00200000) && (true)) {
705 return state->BxBlx_instance_;
706 }
707
708 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00600000) && (true)) {
709 return state->DataProc_instance_;
710 }
711
712 if (((insn & 0x00000070) == 0x00000020) && ((insn & 0x00600000) == 0x00200000) && (true)) {
713 return state->Forbidden_instance_;
714 }
715
716 if (((insn & 0x00000070) == 0x00000030) && ((insn & 0x00600000) == 0x00200000) && (true)) {
717 return state->BxBlx_instance_;
718 }
719
720 if (((insn & 0x00000070) == 0x00000050) && (true) && (true)) {
721 return decode_sat_add_sub(insn, state);
722 }
723
724 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00200000) && (true)) {
725 return state->Breakpoint_instance_;
726 }
727
728 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00600000) && (true)) {
729 return state->Forbidden_instance_;
730 }
731
732 if ((true) && (true) && (true)) {
733 return state->Undefined_instance_;
734 }
735
736 // Catch any attempt to fall through...
737 fprintf(stderr, "TABLE IS INCOMPLETE: misc could not parse %08X",insn.bits(31, 0));
738 return state->Forbidden_instance_;
739 }
740
741 /*
742 * Implementation of table load_store_word_byte.
743 * Specified by: See Section A5.3.
744 */
745 static inline const ClassDecoder &decode_load_store_word_byte(
746 const Instruction insn, const NamedArm32DecoderState *state) {
747 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && (true)) {
748 return state->Forbidden_instance_;
749 }
750
751 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00000000) && (true)) {
752 return state->StoreImmediate_instance_;
753 }
754
755 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00100000) && (true)) {
756 return state->LoadImmediate_instance_;
757 }
758
759 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x00000010) == 0x00000000)) {
760 return state->Forbidden_instance_;
761 }
762
763 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
764 return state->StoreRegister_instance_;
765 }
766
767 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000010) == 0x00000000)) {
768 return state->LoadRegister_instance_;
769 }
770
771 // Catch any attempt to fall through...
772 fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08 X",insn.bits(31,0));
773 return state->Forbidden_instance_;
774 }
775
776 /*
777 * Implementation of table media.
778 * Specified by: See Section A5.4.
779 */
780 static inline const ClassDecoder &decode_media(
781 const Instruction insn, const NamedArm32DecoderState *state) {
782 if (((insn & 0x01F00000) == 0x01800000) && ((insn & 0x000000E0) == 0x00000000) ) {
783 return state->Multiply_instance_;
784 }
785
786 if (((insn & 0x01F00000) == 0x01F00000) && ((insn & 0x000000E0) == 0x000000E0) ) {
787 return state->Roadblock_instance_;
788 }
789
790 if (((insn & 0x01E00000) == 0x01C00000) && ((insn & 0x00000060) == 0x00000000) ) {
791 return state->DataProc_instance_;
792 }
793
794 if (((insn & 0x01A00000) == 0x01A00000) && ((insn & 0x00000060) == 0x00000040) ) {
795 return state->DataProc_instance_;
796 }
797
798 if (((insn & 0x01800000) == 0x00000000) && (true)) {
799 return decode_parallel_add_sub(insn, state);
800 }
801
802 if (((insn & 0x01800000) == 0x00800000) && (true)) {
803 return decode_pack_sat_rev(insn, state);
804 }
805
806 if (((insn & 0x01800000) == 0x01000000) && (true)) {
807 return decode_signed_mult(insn, state);
808 }
809
810 if ((true) && (true)) {
811 return state->Undefined_instance_;
812 }
813
814 // Catch any attempt to fall through...
815 fprintf(stderr, "TABLE IS INCOMPLETE: media could not parse %08X",insn.bits(31 ,0));
816 return state->Forbidden_instance_;
817 }
818
819 /*
820 * Implementation of table parallel_add_sub.
821 * Specified by: See Sections A5.4.1, A5.4.2.
822 */
823 static inline const ClassDecoder &decode_parallel_add_sub(
824 const Instruction insn, const NamedArm32DecoderState *state) {
825 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000080) ) {
826 return state->DataProc_instance_;
827 }
828
829 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x000000E0) ) {
830 return state->DataProc_instance_;
831 }
832
833 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x00000080) == 0x00000000) ) {
834 return state->DataProc_instance_;
835 }
836
837 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x00000080) ) {
838 return state->DataProc_instance_;
839 }
840
841 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x000000E0) ) {
842 return state->DataProc_instance_;
843 }
844
845 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000080) == 0x00000000) ) {
846 return state->DataProc_instance_;
847 }
848
849 if ((true) && (true)) {
850 return state->Undefined_instance_;
851 }
852
853 // Catch any attempt to fall through...
854 fprintf(stderr, "TABLE IS INCOMPLETE: parallel_add_sub could not parse %08X",i nsn.bits(31,0));
855 return state->Forbidden_instance_;
856 }
857
858 /*
859 * Implementation of table pack_sat_rev.
860 * Specified by: See Section A5.4.3.
861 */
862 static inline const ClassDecoder &decode_pack_sat_rev(
863 const Instruction insn, const NamedArm32DecoderState *state) {
864 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000E0) == 0x000000A0) ) {
865 return state->PackSatRev_instance_;
866 }
867
868 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000020) == 0x00000000) ) {
869 return state->PackSatRev_instance_;
870 }
871
872 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x000000E0) == 0x00000060) ) {
873 return state->PackSatRev_instance_;
874 }
875
876 if (((insn & 0x00700000) == 0x00600000) && ((insn & 0x000000A0) == 0x00000020) ) {
877 return state->PackSatRev_instance_;
878 }
879
880 if (((insn & 0x00700000) == 0x00700000) && ((insn & 0x000000E0) == 0x00000020) ) {
881 return state->PackSatRev_instance_;
882 }
883
884 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x00000060) ) {
885 return state->PackSatRev_instance_;
886 }
887
888 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x000000A0) ) {
889 return state->PackSatRev_instance_;
890 }
891
892 if (((insn & 0x00500000) == 0x00000000) && ((insn & 0x000000E0) == 0x00000060) ) {
893 return state->PackSatRev_instance_;
894 }
895
896 if (((insn & 0x00600000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000020) ) {
897 return state->PackSatRev_instance_;
898 }
899
900 if (((insn & 0x00200000) == 0x00200000) && ((insn & 0x00000020) == 0x00000000) ) {
901 return state->PackSatRev_instance_;
902 }
903
904 if ((true) && (true)) {
905 return state->Undefined_instance_;
906 }
907
908 // Catch any attempt to fall through...
909 fprintf(stderr, "TABLE IS INCOMPLETE: pack_sat_rev could not parse %08X",insn. bits(31,0));
910 return state->Forbidden_instance_;
911 }
912
913 /*
914 * Implementation of table signed_mult.
915 * Specified by: See Section A5.4.4.
916 */
917 static inline const ClassDecoder &decode_signed_mult(
918 const Instruction insn, const NamedArm32DecoderState *state) {
919 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000C0) == 0x00000040) && ((insn & 0x0000F000) != 0x0000F000)) {
920 return state->Multiply_instance_;
921 }
922
923 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
924 return state->Multiply_instance_;
925 }
926
927 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
928 return state->LongMultiply_instance_;
929 }
930
931 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x00000000) && (true)) {
932 return state->Multiply_instance_;
933 }
934
935 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x000000C0) && (true)) {
936 return state->Multiply_instance_;
937 }
938
939 if ((true) && (true) && (true)) {
940 return state->Undefined_instance_;
941 }
942
943 // Catch any attempt to fall through...
944 fprintf(stderr, "TABLE IS INCOMPLETE: signed_mult could not parse %08X",insn.b its(31,0));
945 return state->Forbidden_instance_;
946 }
947
948 /*
949 * Implementation of table branch_block_xfer.
950 * Specified by: See Section A5.5.
951 */
952 static inline const ClassDecoder &decode_branch_block_xfer(
953 const Instruction insn, const NamedArm32DecoderState *state) {
954 if (((insn & 0x02500000) == 0x00000000)) {
955 return state->StoreImmediate_instance_;
956 }
957
958 if (((insn & 0x02500000) == 0x00100000)) {
959 return state->LoadMultiple_instance_;
960 }
961
962 if (((insn & 0x02400000) == 0x00400000)) {
963 return state->Forbidden_instance_;
964 }
965
966 if (((insn & 0x02000000) == 0x02000000)) {
967 return state->Branch_instance_;
968 }
969
970 // Catch any attempt to fall through...
971 fprintf(stderr, "TABLE IS INCOMPLETE: branch_block_xfer could not parse %08X", insn.bits(31,0));
972 return state->Forbidden_instance_;
973 }
974
975 /*
976 * Implementation of table super_cop.
977 * Specified by: See Section A5.6.
978 */
979 static inline const ClassDecoder &decode_super_cop(
980 const Instruction insn, const NamedArm32DecoderState *state) {
981 if (((insn & 0x03F00000) == 0x00400000) && (true)) {
982 return state->CoprocessorOp_instance_;
983 }
984
985 if (((insn & 0x03F00000) == 0x00500000) && (true)) {
986 return state->MoveDoubleFromCoprocessor_instance_;
987 }
988
989 if (((insn & 0x03E00000) == 0x00000000) && (true)) {
990 return state->Undefined_instance_;
991 }
992
993 if (((insn & 0x03100000) == 0x02000000) && ((insn & 0x00000010) == 0x00000010) ) {
994 return state->CoprocessorOp_instance_;
995 }
996
997 if (((insn & 0x03100000) == 0x02100000) && ((insn & 0x00000010) == 0x00000010) ) {
998 return state->MoveFromCoprocessor_instance_;
999 }
1000
1001 if (((insn & 0x02100000) == 0x00000000) && (true)) {
1002 return state->StoreCoprocessor_instance_;
1003 }
1004
1005 if (((insn & 0x02100000) == 0x00100000) && (true)) {
1006 return state->LoadCoprocessor_instance_;
1007 }
1008
1009 if (((insn & 0x03000000) == 0x02000000) && ((insn & 0x00000010) == 0x00000000) ) {
1010 return state->CoprocessorOp_instance_;
1011 }
1012
1013 if (((insn & 0x03000000) == 0x03000000) && (true)) {
1014 return state->Forbidden_instance_;
1015 }
1016
1017 // Catch any attempt to fall through...
1018 fprintf(stderr, "TABLE IS INCOMPLETE: super_cop could not parse %08X",insn.bit s(31,0));
1019 return state->Forbidden_instance_;
1020 }
1021
1022 /*
1023 * Implementation of table unconditional.
1024 * Specified by: See Section A5.7.
1025 */
1026 static inline const ClassDecoder &decode_unconditional(
1027 const Instruction insn, const NamedArm32DecoderState *state) {
1028 if (((insn & 0x0FF00000) == 0x0C400000) && (true) && (true)) { 1568 if (((insn & 0x0FF00000) == 0x0C400000) && (true) && (true)) {
1029 return state->CoprocessorOp_instance_; 1569 return CoprocessorOp_instance_;
1030 } 1570 }
1031 1571
1032 if (((insn & 0x0FF00000) == 0x0C500000) && (true) && (true)) { 1572 if (((insn & 0x0E500000) == 0x08400000) && (true) && (true)) {
1033 return state->MoveDoubleFromCoprocessor_instance_; 1573 return Forbidden_instance_;
1034 } 1574 }
1035 1575
1036 if (((insn & 0x0FB00000) == 0x0C200000) && (true) && (true)) {
1037 return state->StoreCoprocessor_instance_;
1038 }
1039
1040 if (((insn & 0x0FB00000) == 0x0C300000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
1041 return state->LoadCoprocessor_instance_;
1042 }
1043
1044 if (((insn & 0x0F900000) == 0x0C800000) && (true) && (true)) {
1045 return state->StoreCoprocessor_instance_;
1046 }
1047
1048 if (((insn & 0x0F900000) == 0x0C900000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
1049 return state->LoadCoprocessor_instance_;
1050 }
1051
1052 if (((insn & 0x0E500000) == 0x08100000) && (true) && (true)) { 1576 if (((insn & 0x0E500000) == 0x08100000) && (true) && (true)) {
1053 return state->Forbidden_instance_; 1577 return Forbidden_instance_;
1054 } 1578 }
1055 1579
1056 if (((insn & 0x0E500000) == 0x08400000) && (true) && (true)) {
1057 return state->Forbidden_instance_;
1058 }
1059
1060 if (((insn & 0x0F100000) == 0x0D000000) && (true) && (true)) {
1061 return state->StoreCoprocessor_instance_;
1062 }
1063
1064 if (((insn & 0x0F100000) == 0x0D100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
1065 return state->LoadCoprocessor_instance_;
1066 }
1067
1068 if (((insn & 0x0F100000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
1069 return state->CoprocessorOp_instance_;
1070 }
1071
1072 if (((insn & 0x0F100000) == 0x0E100000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
1073 return state->MoveFromCoprocessor_instance_;
1074 }
1075
1076 if (((insn & 0x0F000000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1077 return state->CoprocessorOp_instance_;
1078 }
1079
1080 if (((insn & 0x0E000000) == 0x0A000000) && (true) && (true)) { 1580 if (((insn & 0x0E000000) == 0x0A000000) && (true) && (true)) {
1081 return state->Forbidden_instance_; 1581 return Forbidden_instance_;
1082 } 1582 }
1083 1583
1084 if (((insn & 0x08000000) == 0x00000000) && (true) && (true)) { 1584 // Catch any attempt to fall through...
1085 return decode_misc_hints_simd(insn, state); 1585 fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",
1086 } 1586 insn.bits(31,0));
1087 1587 return Forbidden_instance_;
1088 if ((true) && (true) && (true)) { 1588 }
1089 return state->Undefined_instance_; 1589
1090 } 1590
1091 1591 const NamedClassDecoder& NamedArm32DecoderState::
1092 // Catch any attempt to fall through... 1592 decode_named(const nacl_arm_dec::Instruction insn) const {
1093 fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",insn .bits(31,0)); 1593 return decode_ARMv7(insn);
1094 return state->Forbidden_instance_; 1594 }
1095 } 1595
1096 1596 const nacl_arm_dec::ClassDecoder& NamedArm32DecoderState::
1097 /* 1597 decode(const nacl_arm_dec::Instruction insn) const {
1098 * Implementation of table misc_hints_simd. 1598 return decode_named(insn).named_decoder();
1099 * Specified by: See Section A5.7.1. 1599 }
1100 */ 1600
1101 static inline const ClassDecoder &decode_misc_hints_simd( 1601 } // namespace nacl_arm_test
1102 const Instruction insn, const NamedArm32DecoderState *state) {
1103 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000000) && ((insn & 0x00010000) == 0x00010000)) {
1104 return state->Forbidden_instance_;
1105 }
1106
1107 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x00000020) == 0x00000000) && ((insn & 0x00010000) == 0x00000000)) {
1108 return state->Forbidden_instance_;
1109 }
1110
1111 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000010) && (true)) {
1112 return state->EffectiveNoOp_instance_;
1113 }
1114
1115 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000050) && (true)) {
1116 return state->EffectiveNoOp_instance_;
1117 }
1118
1119 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000D0) == 0x00000040) && (true)) {
1120 return state->EffectiveNoOp_instance_;
1121 }
1122
1123 if (((insn & 0x07700000) == 0x04100000) && (true) && (true)) {
1124 return state->EffectiveNoOp_instance_;
1125 }
1126
1127 if (((insn & 0x07700000) == 0x04500000) && (true) && (true)) {
1128 return state->EffectiveNoOp_instance_;
1129 }
1130
1131 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
1132 return state->EffectiveNoOp_instance_;
1133 }
1134
1135 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
1136 return state->Unpredictable_instance_;
1137 }
1138
1139 if (((insn & 0x07700000) == 0x05500000) && (true) && (true)) {
1140 return state->EffectiveNoOp_instance_;
1141 }
1142
1143 if (((insn & 0x07700000) == 0x06500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1144 return state->EffectiveNoOp_instance_;
1145 }
1146
1147 if (((insn & 0x07700000) == 0x07500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1148 return state->EffectiveNoOp_instance_;
1149 }
1150
1151 if (((insn & 0x06700000) == 0x06100000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1152 return state->EffectiveNoOp_instance_;
1153 }
1154
1155 if (((insn & 0x06300000) == 0x04300000) && (true) && (true)) {
1156 return state->Unpredictable_instance_;
1157 }
1158
1159 if (((insn & 0x06300000) == 0x06300000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1160 return state->Unpredictable_instance_;
1161 }
1162
1163 if (((insn & 0x07100000) == 0x04000000) && (true) && (true)) {
1164 return decode_simd_load_store(insn, state);
1165 }
1166
1167 if (((insn & 0x06000000) == 0x02000000) && (true) && (true)) {
1168 return decode_simd_dp(insn, state);
1169 }
1170
1171 if ((true) && (true) && (true)) {
1172 return state->Undefined_instance_;
1173 }
1174
1175 // Catch any attempt to fall through...
1176 fprintf(stderr, "TABLE IS INCOMPLETE: misc_hints_simd could not parse %08X",in sn.bits(31,0));
1177 return state->Forbidden_instance_;
1178 }
1179
1180 /*
1181 * Implementation of table simd_dp.
1182 * Specified by: See Section A7.4.
1183 */
1184 static inline const ClassDecoder &decode_simd_dp(
1185 const Instruction insn, const NamedArm32DecoderState *state) {
1186 if (((insn & 0x01000000) == 0x00000000) && ((insn & 0x00B00000) == 0x00B00000) && (true) && ((insn & 0x00000010) == 0x00000000)) {
1187 return state->EffectiveNoOp_instance_;
1188 }
1189
1190 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000F00) == 0x00000C00) && ((insn & 0x00000090) == 0x00000000)) {
1191 return state->EffectiveNoOp_instance_;
1192 }
1193
1194 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000C00) == 0x00000800) && ((insn & 0x00000010) == 0x00000000)) {
1195 return state->EffectiveNoOp_instance_;
1196 }
1197
1198 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000800) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
1199 return decode_simd_dp_2misc(insn, state);
1200 }
1201
1202 if ((true) && ((insn & 0x00B80000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1203 return decode_simd_dp_1imm(insn, state);
1204 }
1205
1206 if ((true) && ((insn & 0x00B80000) == 0x00880000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1207 return decode_simd_dp_2shift(insn, state);
1208 }
1209
1210 if ((true) && ((insn & 0x00B00000) == 0x00900000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1211 return decode_simd_dp_2shift(insn, state);
1212 }
1213
1214 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
1215 return decode_simd_dp_3diff(insn, state);
1216 }
1217
1218 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
1219 return decode_simd_dp_2scalar(insn, state);
1220 }
1221
1222 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
1223 return decode_simd_dp_3diff(insn, state);
1224 }
1225
1226 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
1227 return decode_simd_dp_2scalar(insn, state);
1228 }
1229
1230 if ((true) && ((insn & 0x00A00000) == 0x00A00000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1231 return decode_simd_dp_2shift(insn, state);
1232 }
1233
1234 if ((true) && ((insn & 0x00800000) == 0x00000000) && (true) && (true)) {
1235 return decode_simd_dp_3same(insn, state);
1236 }
1237
1238 if ((true) && ((insn & 0x00800000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000090)) {
1239 return decode_simd_dp_2shift(insn, state);
1240 }
1241
1242 if ((true) && (true) && (true) && (true)) {
1243 return state->Undefined_instance_;
1244 }
1245
1246 // Catch any attempt to fall through...
1247 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp could not parse %08X",insn.bits( 31,0));
1248 return state->Forbidden_instance_;
1249 }
1250
1251 /*
1252 * Implementation of table simd_dp_3same.
1253 * Specified by: See Section A7.4.1.
1254 */
1255 static inline const ClassDecoder &decode_simd_dp_3same(
1256 const Instruction insn, const NamedArm32DecoderState *state) {
1257 if (((insn & 0x00000F00) == 0x00000100) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1258 return state->EffectiveNoOp_instance_;
1259 }
1260
1261 if (((insn & 0x00000F00) == 0x00000500) && (true) && (true) && (true)) {
1262 return state->EffectiveNoOp_instance_;
1263 }
1264
1265 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1266 return state->EffectiveNoOp_instance_;
1267 }
1268
1269 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1270 return state->EffectiveNoOp_instance_;
1271 }
1272
1273 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1274 return state->EffectiveNoOp_instance_;
1275 }
1276
1277 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00000000)) {
1278 return state->EffectiveNoOp_instance_;
1279 }
1280
1281 if (((insn & 0x00000F00) == 0x00000D00) && (true) && ((insn & 0x01000000) == 0 x00000000) && (true)) {
1282 return state->EffectiveNoOp_instance_;
1283 }
1284
1285 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00200000)) {
1286 return state->EffectiveNoOp_instance_;
1287 }
1288
1289 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && (true) && ((insn & 0x00200000) == 0x00000000)) {
1290 return state->EffectiveNoOp_instance_;
1291 }
1292
1293 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1294 return state->EffectiveNoOp_instance_;
1295 }
1296
1297 if (((insn & 0x00000700) == 0x00000700) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1298 return state->EffectiveNoOp_instance_;
1299 }
1300
1301 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1302 return state->EffectiveNoOp_instance_;
1303 }
1304
1305 if (((insn & 0x00000B00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x00000000) && (true)) {
1306 return state->EffectiveNoOp_instance_;
1307 }
1308
1309 if (((insn & 0x00000D00) == 0x00000100) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1310 return state->EffectiveNoOp_instance_;
1311 }
1312
1313 if (((insn & 0x00000D00) == 0x00000800) && (true) && (true) && (true)) {
1314 return state->EffectiveNoOp_instance_;
1315 }
1316
1317 if (((insn & 0x00000900) == 0x00000000) && (true) && (true) && (true)) {
1318 return state->EffectiveNoOp_instance_;
1319 }
1320
1321 if ((true) && (true) && (true) && (true)) {
1322 return state->Undefined_instance_;
1323 }
1324
1325 // Catch any attempt to fall through...
1326 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3same could not parse %08X",insn .bits(31,0));
1327 return state->Forbidden_instance_;
1328 }
1329
1330 /*
1331 * Implementation of table simd_dp_3diff.
1332 * Specified by: See Section A7.4.2.
1333 */
1334 static inline const ClassDecoder &decode_simd_dp_3diff(
1335 const Instruction insn, const NamedArm32DecoderState *state) {
1336 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x01000000) == 0x00000000) ) {
1337 return state->EffectiveNoOp_instance_;
1338 }
1339
1340 if (((insn & 0x00000D00) == 0x00000900) && ((insn & 0x01000000) == 0x00000000) ) {
1341 return state->EffectiveNoOp_instance_;
1342 }
1343
1344 if (((insn & 0x00000900) == 0x00000800) && (true)) {
1345 return state->EffectiveNoOp_instance_;
1346 }
1347
1348 if (((insn & 0x00000800) == 0x00000000) && (true)) {
1349 return state->EffectiveNoOp_instance_;
1350 }
1351
1352 if ((true) && (true)) {
1353 return state->Undefined_instance_;
1354 }
1355
1356 // Catch any attempt to fall through...
1357 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3diff could not parse %08X",insn .bits(31,0));
1358 return state->Forbidden_instance_;
1359 }
1360
1361 /*
1362 * Implementation of table simd_dp_2scalar.
1363 * Specified by: See Section A7.4.3.
1364 */
1365 static inline const ClassDecoder &decode_simd_dp_2scalar(
1366 const Instruction insn, const NamedArm32DecoderState *state) {
1367 if (((insn & 0x00000F00) == 0x00000A00) && (true)) {
1368 return state->EffectiveNoOp_instance_;
1369 }
1370
1371 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x01000000) == 0x00000000) ) {
1372 return state->EffectiveNoOp_instance_;
1373 }
1374
1375 if (((insn & 0x00000B00) == 0x00000200) && (true)) {
1376 return state->EffectiveNoOp_instance_;
1377 }
1378
1379 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x01000000) == 0x00000000) ) {
1380 return state->EffectiveNoOp_instance_;
1381 }
1382
1383 if (((insn & 0x00000200) == 0x00000000) && (true)) {
1384 return state->EffectiveNoOp_instance_;
1385 }
1386
1387 if ((true) && (true)) {
1388 return state->Undefined_instance_;
1389 }
1390
1391 // Catch any attempt to fall through...
1392 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2scalar could not parse %08X",in sn.bits(31,0));
1393 return state->Forbidden_instance_;
1394 }
1395
1396 /*
1397 * Implementation of table simd_dp_2shift.
1398 * Specified by: See Section A7.4.4.
1399 */
1400 static inline const ClassDecoder &decode_simd_dp_2shift(
1401 const Instruction insn, const NamedArm32DecoderState *state) {
1402 if (((insn & 0x00000F00) == 0x00000500) && ((insn & 0x01000000) == 0x00000000) && (true) && (true)) {
1403 return state->EffectiveNoOp_instance_;
1404 }
1405
1406 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x00000040) == 0x00000000) && ((insn & 0x00000080) == 0x00000000)) {
1407 return state->EffectiveNoOp_instance_;
1408 }
1409
1410 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00000040) == 0x00000000) && (true)) {
1411 return state->EffectiveNoOp_instance_;
1412 }
1413
1414 if (((insn & 0x00000F00) == 0x00000800) && (true) && ((insn & 0x00000040) == 0 x00000040) && (true)) {
1415 return state->EffectiveNoOp_instance_;
1416 }
1417
1418 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1419 return state->EffectiveNoOp_instance_;
1420 }
1421
1422 if (((insn & 0x00000F00) == 0x00000A00) && (true) && ((insn & 0x00000040) == 0 x00000000) && (true)) {
1423 return state->EffectiveNoOp_instance_;
1424 }
1425
1426 if (((insn & 0x00000E00) == 0x00000400) && ((insn & 0x01000000) == 0x01000000) && (true) && (true)) {
1427 return state->EffectiveNoOp_instance_;
1428 }
1429
1430 if (((insn & 0x00000600) == 0x00000600) && (true) && (true) && (true)) {
1431 return state->EffectiveNoOp_instance_;
1432 }
1433
1434 if (((insn & 0x00000C00) == 0x00000000) && (true) && (true) && (true)) {
1435 return state->EffectiveNoOp_instance_;
1436 }
1437
1438 if ((true) && (true) && (true) && (true)) {
1439 return state->Undefined_instance_;
1440 }
1441
1442 // Catch any attempt to fall through...
1443 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2shift could not parse %08X",ins n.bits(31,0));
1444 return state->Forbidden_instance_;
1445 }
1446
1447 /*
1448 * Implementation of table simd_dp_2misc.
1449 * Specified by: See Section A7.4.5.
1450 */
1451 static inline const ClassDecoder &decode_simd_dp_2misc(
1452 const Instruction insn, const NamedArm32DecoderState *state) {
1453 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000780) == 0x00000700) ) {
1454 return state->EffectiveNoOp_instance_;
1455 }
1456
1457 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000380) == 0x00000100) ) {
1458 return state->EffectiveNoOp_instance_;
1459 }
1460
1461 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000580) == 0x00000580) ) {
1462 return state->EffectiveNoOp_instance_;
1463 }
1464
1465 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000100) == 0x00000000) ) {
1466 return state->EffectiveNoOp_instance_;
1467 }
1468
1469 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000380) == 0x00000380) ) {
1470 return state->EffectiveNoOp_instance_;
1471 }
1472
1473 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000280) == 0x00000200) ) {
1474 return state->EffectiveNoOp_instance_;
1475 }
1476
1477 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000200) == 0x00000000) ) {
1478 return state->EffectiveNoOp_instance_;
1479 }
1480
1481 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000007C0) == 0x00000300) ) {
1482 return state->EffectiveNoOp_instance_;
1483 }
1484
1485 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000006C0) == 0x00000600) ) {
1486 return state->EffectiveNoOp_instance_;
1487 }
1488
1489 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000700) == 0x00000200) ) {
1490 return state->EffectiveNoOp_instance_;
1491 }
1492
1493 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000600) == 0x00000000) ) {
1494 return state->EffectiveNoOp_instance_;
1495 }
1496
1497 if (((insn & 0x00030000) == 0x00030000) && ((insn & 0x00000400) == 0x00000400) ) {
1498 return state->EffectiveNoOp_instance_;
1499 }
1500
1501 if ((true) && (true)) {
1502 return state->Undefined_instance_;
1503 }
1504
1505 // Catch any attempt to fall through...
1506 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2misc could not parse %08X",insn .bits(31,0));
1507 return state->Forbidden_instance_;
1508 }
1509
1510 /*
1511 * Implementation of table simd_dp_1imm.
1512 * Specified by: See Section A7.4.6.
1513 */
1514 static inline const ClassDecoder &decode_simd_dp_1imm(
1515 const Instruction insn, const NamedArm32DecoderState *state) {
1516 if (((insn & 0x00000020) == 0x00000000) && (true)) {
1517 return state->EffectiveNoOp_instance_;
1518 }
1519
1520 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000E00) ) {
1521 return state->EffectiveNoOp_instance_;
1522 }
1523
1524 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000F00) ) {
1525 return state->Undefined_instance_;
1526 }
1527
1528 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000E00) == 0x00000C00) ) {
1529 return state->EffectiveNoOp_instance_;
1530 }
1531
1532 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000C00) == 0x00000800) ) {
1533 return state->EffectiveNoOp_instance_;
1534 }
1535
1536 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000800) == 0x00000000) ) {
1537 return state->EffectiveNoOp_instance_;
1538 }
1539
1540 // Catch any attempt to fall through...
1541 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_1imm could not parse %08X",insn. bits(31,0));
1542 return state->Forbidden_instance_;
1543 }
1544
1545 /*
1546 * Implementation of table simd_load_store.
1547 * Specified by: See Section A7.7.
1548 */
1549 static inline const ClassDecoder &decode_simd_load_store(
1550 const Instruction insn, const NamedArm32DecoderState *state) {
1551 if (((insn & 0x00200000) == 0x00000000)) {
1552 return decode_simd_load_store_l0(insn, state);
1553 }
1554
1555 if (((insn & 0x00200000) == 0x00200000)) {
1556 return decode_simd_load_store_l1(insn, state);
1557 }
1558
1559 // Catch any attempt to fall through...
1560 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store could not parse %08X",in sn.bits(31,0));
1561 return state->Forbidden_instance_;
1562 }
1563
1564 /*
1565 * Implementation of table simd_load_store_l0.
1566 * Specified by: See Section A7.7, Table A7-20.
1567 */
1568 static inline const ClassDecoder &decode_simd_load_store_l0(
1569 const Instruction insn, const NamedArm32DecoderState *state) {
1570 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1571 return state->VectorStore_instance_;
1572 }
1573
1574 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1575 return state->VectorStore_instance_;
1576 }
1577
1578 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1579 return state->VectorStore_instance_;
1580 }
1581
1582 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1583 return state->VectorStore_instance_;
1584 }
1585
1586 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000C00) == 0x00000800) ) {
1587 return state->VectorStore_instance_;
1588 }
1589
1590 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000800) == 0x00000000) ) {
1591 return state->VectorStore_instance_;
1592 }
1593
1594 if ((true) && (true)) {
1595 return state->Undefined_instance_;
1596 }
1597
1598 // Catch any attempt to fall through...
1599 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l0 could not parse %08X" ,insn.bits(31,0));
1600 return state->Forbidden_instance_;
1601 }
1602
1603 /*
1604 * Implementation of table simd_load_store_l1.
1605 * Specified by: See Section A7.7, Table A7-21.
1606 */
1607 static inline const ClassDecoder &decode_simd_load_store_l1(
1608 const Instruction insn, const NamedArm32DecoderState *state) {
1609 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1610 return state->VectorLoad_instance_;
1611 }
1612
1613 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1614 return state->VectorLoad_instance_;
1615 }
1616
1617 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1618 return state->VectorLoad_instance_;
1619 }
1620
1621 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1622 return state->VectorLoad_instance_;
1623 }
1624
1625 if (((insn & 0x00800000) == 0x00800000) && (true)) {
1626 return state->VectorLoad_instance_;
1627 }
1628
1629 if ((true) && (true)) {
1630 return state->Undefined_instance_;
1631 }
1632
1633 // Catch any attempt to fall through...
1634 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l1 could not parse %08X" ,insn.bits(31,0));
1635 return state->Forbidden_instance_;
1636 }
1637
1638 NamedArm32DecoderState::NamedArm32DecoderState() :
1639 DecoderState()
1640 , CoprocessorOp_instance_()
1641 , ImmediateBic_instance_()
1642 , LoadMultiple_instance_()
1643 , LoadCoprocessor_instance_()
1644 , LoadDoubleExclusive_instance_()
1645 , Branch_instance_()
1646 , Test_instance_()
1647 , StoreRegister_instance_()
1648 , MoveDoubleFromCoprocessor_instance_()
1649 , TestImmediate_instance_()
1650 , BxBlx_instance_()
1651 , EffectiveNoOp_instance_()
1652 , LongMultiply_instance_()
1653 , Binary4RegisterShiftedOp_instance_()
1654 , Breakpoint_instance_()
1655 , Multiply_instance_()
1656 , PackSatRev_instance_()
1657 , LoadExclusive_instance_()
1658 , VectorStore_instance_()
1659 , Unary3RegisterShiftedOp_instance_()
1660 , Undefined_instance_()
1661 , DataProc_instance_()
1662 , Deprecated_instance_()
1663 , LoadImmediate_instance_()
1664 , StoreCoprocessor_instance_()
1665 , Roadblock_instance_()
1666 , LoadDoubleR_instance_()
1667 , StoreExclusive_instance_()
1668 , StoreImmediate_instance_()
1669 , MoveFromCoprocessor_instance_()
1670 , LoadRegister_instance_()
1671 , LoadDoubleI_instance_()
1672 , Binary3RegisterShiftedTest_instance_()
1673 , Unpredictable_instance_()
1674 , Forbidden_instance_()
1675 , VectorLoad_instance_()
1676 , MoveToStatusRegister_instance_()
1677 , SatAddSub_instance_()
1678 {
1679 }
1680
1681 NamedArm32DecoderState::~NamedArm32DecoderState() {
1682 }
1683
1684 const ClassDecoder &NamedArm32DecoderState::decode(const Instruction insn) const {
1685 return decode_ARMv7(insn, this);
1686 }
1687
1688 } // namespace
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