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Side by Side Diff: src/trusted/validator_arm/gen/arm32_decode.cc

Issue 9960043: Finish separation of testing from sel_ldr validation. Also, automate (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 8 months ago
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1 /* 3 /*
2 * Copyright 2012 The Native Client Authors. All rights reserved. 4 * Copyright 2012 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can 5 * Use of this source code is governed by a BSD-style license that can
4 * be found in the LICENSE file. 6 * be found in the LICENSE file.
5 */ 7 */
6 8
7 /* 9 // DO NOT EDIT: GENERATED CODE
8 * DO NOT EDIT: GENERATED CODE 10
9 */
10 11
11 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h" 12 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h"
12 13
13 #include <stdio.h> 14 #include <stdio.h>
14 15
15 namespace nacl_arm_dec { 16 namespace nacl_arm_dec {
16 17
17 /* 18
18 * Prototypes for static table-matching functions. 19 Arm32DecoderState::Arm32DecoderState() : DecoderState()
19 */ 20
20 static inline const ClassDecoder &decode_ARMv7( 21 , Binary3RegisterShiftedTest_instance_()
21 const Instruction insn, const Arm32DecoderState *state); 22
22 23 , Binary4RegisterShiftedOp_instance_()
23 static inline const ClassDecoder &decode_dp_misc( 24
24 const Instruction insn, const Arm32DecoderState *state); 25 , Branch_instance_()
25 26
26 static inline const ClassDecoder &decode_dp_reg( 27 , Breakpoint_instance_()
27 const Instruction insn, const Arm32DecoderState *state); 28
28 29 , BxBlx_instance_()
29 static inline const ClassDecoder &decode_dp_reg_shifted( 30
30 const Instruction insn, const Arm32DecoderState *state);
31
32 static inline const ClassDecoder &decode_dp_immed(
33 const Instruction insn, const Arm32DecoderState *state);
34
35 static inline const ClassDecoder &decode_mult(
36 const Instruction insn, const Arm32DecoderState *state);
37
38 static inline const ClassDecoder &decode_sat_add_sub(
39 const Instruction insn, const Arm32DecoderState *state);
40
41 static inline const ClassDecoder &decode_half_mult(
42 const Instruction insn, const Arm32DecoderState *state);
43
44 static inline const ClassDecoder &decode_extra_load_store(
45 const Instruction insn, const Arm32DecoderState *state);
46
47 static inline const ClassDecoder &decode_sync(
48 const Instruction insn, const Arm32DecoderState *state);
49
50 static inline const ClassDecoder &decode_msr_and_hints(
51 const Instruction insn, const Arm32DecoderState *state);
52
53 static inline const ClassDecoder &decode_misc(
54 const Instruction insn, const Arm32DecoderState *state);
55
56 static inline const ClassDecoder &decode_load_store_word_byte(
57 const Instruction insn, const Arm32DecoderState *state);
58
59 static inline const ClassDecoder &decode_media(
60 const Instruction insn, const Arm32DecoderState *state);
61
62 static inline const ClassDecoder &decode_parallel_add_sub(
63 const Instruction insn, const Arm32DecoderState *state);
64
65 static inline const ClassDecoder &decode_pack_sat_rev(
66 const Instruction insn, const Arm32DecoderState *state);
67
68 static inline const ClassDecoder &decode_signed_mult(
69 const Instruction insn, const Arm32DecoderState *state);
70
71 static inline const ClassDecoder &decode_branch_block_xfer(
72 const Instruction insn, const Arm32DecoderState *state);
73
74 static inline const ClassDecoder &decode_super_cop(
75 const Instruction insn, const Arm32DecoderState *state);
76
77 static inline const ClassDecoder &decode_unconditional(
78 const Instruction insn, const Arm32DecoderState *state);
79
80 static inline const ClassDecoder &decode_misc_hints_simd(
81 const Instruction insn, const Arm32DecoderState *state);
82
83 static inline const ClassDecoder &decode_simd_dp(
84 const Instruction insn, const Arm32DecoderState *state);
85
86 static inline const ClassDecoder &decode_simd_dp_3same(
87 const Instruction insn, const Arm32DecoderState *state);
88
89 static inline const ClassDecoder &decode_simd_dp_3diff(
90 const Instruction insn, const Arm32DecoderState *state);
91
92 static inline const ClassDecoder &decode_simd_dp_2scalar(
93 const Instruction insn, const Arm32DecoderState *state);
94
95 static inline const ClassDecoder &decode_simd_dp_2shift(
96 const Instruction insn, const Arm32DecoderState *state);
97
98 static inline const ClassDecoder &decode_simd_dp_2misc(
99 const Instruction insn, const Arm32DecoderState *state);
100
101 static inline const ClassDecoder &decode_simd_dp_1imm(
102 const Instruction insn, const Arm32DecoderState *state);
103
104 static inline const ClassDecoder &decode_simd_load_store(
105 const Instruction insn, const Arm32DecoderState *state);
106
107 static inline const ClassDecoder &decode_simd_load_store_l0(
108 const Instruction insn, const Arm32DecoderState *state);
109
110 static inline const ClassDecoder &decode_simd_load_store_l1(
111 const Instruction insn, const Arm32DecoderState *state);
112
113 /*
114 * Table-matching function implementations.
115 */
116
117 /*
118 * Implementation of table ARMv7.
119 * Specified by: See Section A5.1.
120 */
121 static inline const ClassDecoder &decode_ARMv7(
122 const Instruction insn, const Arm32DecoderState *state) {
123 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x04000000) && (true)) {
124 return decode_load_store_word_byte(insn, state);
125 }
126
127 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000000)) {
128 return decode_load_store_word_byte(insn, state);
129 }
130
131 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000010)) {
132 return decode_media(insn, state);
133 }
134
135 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x00000000) && (true)) {
136 return decode_dp_misc(insn, state);
137 }
138
139 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x08000000) && (true)) {
140 return decode_branch_block_xfer(insn, state);
141 }
142
143 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x0C000000) && (true)) {
144 return decode_super_cop(insn, state);
145 }
146
147 if (((insn & 0xF0000000) == 0xF0000000) && (true) && (true)) {
148 return decode_unconditional(insn, state);
149 }
150
151 // Catch any attempt to fall through...
152 fprintf(stderr, "TABLE IS INCOMPLETE: ARMv7 could not parse %08X",insn.bits(31 ,0));
153 return state->Forbidden_instance_;
154 }
155
156 /*
157 * Implementation of table dp_misc.
158 * Specified by: See Section A5.2.
159 */
160 static inline const ClassDecoder &decode_dp_misc(
161 const Instruction insn, const Arm32DecoderState *state) {
162 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000090) == 0x00000010)) {
163 return decode_dp_reg_shifted(insn, state);
164 }
165
166 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000010) == 0x00000000)) {
167 return decode_dp_reg(insn, state);
168 }
169
170 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000090) == 0x00000080)) {
171 return decode_half_mult(insn, state);
172 }
173
174 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000080) == 0x00000000)) {
175 return decode_misc(insn, state);
176 }
177
178 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
179 return decode_extra_load_store(insn, state);
180 }
181
182 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
183 return decode_extra_load_store(insn, state);
184 }
185
186 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
187 return state->Forbidden_instance_;
188 }
189
190 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
191 return state->Forbidden_instance_;
192 }
193
194 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x000000F0) == 0x00000090)) {
195 return decode_mult(insn, state);
196 }
197
198 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000090)) {
199 return decode_sync(insn, state);
200 }
201
202 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01000000) && (true)) {
203 return state->DataProc_instance_;
204 }
205
206 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01200000) && (true)) {
207 return decode_msr_and_hints(insn, state);
208 }
209
210 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01900000) != 0x01000000) && (true)) {
211 return decode_dp_immed(insn, state);
212 }
213
214 // Catch any attempt to fall through...
215 fprintf(stderr, "TABLE IS INCOMPLETE: dp_misc could not parse %08X",insn.bits( 31,0));
216 return state->Forbidden_instance_;
217 }
218
219 /*
220 * Implementation of table dp_reg.
221 * Specified by: See Section A5.2.1.
222 */
223 static inline const ClassDecoder &decode_dp_reg(
224 const Instruction insn, const Arm32DecoderState *state) {
225 if (((insn & 0x01900000) == 0x01100000)) {
226 return state->Test_instance_;
227 }
228
229 if (((insn & 0x01800000) == 0x01800000)) {
230 return state->DataProc_instance_;
231 }
232
233 if (((insn & 0x01000000) == 0x00000000)) {
234 return state->DataProc_instance_;
235 }
236
237 // Catch any attempt to fall through...
238 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",insn.bits(3 1,0));
239 return state->Forbidden_instance_;
240 }
241
242 /*
243 * Implementation of table dp_reg_shifted.
244 * Specified by: See Section A5.2.2.
245 */
246 static inline const ClassDecoder &decode_dp_reg_shifted(
247 const Instruction insn, const Arm32DecoderState *state) {
248 if (((insn & 0x01E00000) == 0x01A00000)) {
249 return state->DataProc_instance_;
250 }
251
252 if (((insn & 0x01E00000) == 0x01E00000)) {
253 return state->Unary3RegisterShiftedOp_instance_;
254 }
255
256 if (((insn & 0x01900000) == 0x01100000)) {
257 return state->Binary3RegisterShiftedTest_instance_;
258 }
259
260 if (((insn & 0x01A00000) == 0x01800000)) {
261 return state->Binary4RegisterShiftedOp_instance_;
262 }
263
264 if (((insn & 0x01000000) == 0x00000000)) {
265 return state->Binary4RegisterShiftedOp_instance_;
266 }
267
268 // Catch any attempt to fall through...
269 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg_shifted could not parse %08X",ins n.bits(31,0));
270 return state->Forbidden_instance_;
271 }
272
273 /*
274 * Implementation of table dp_immed.
275 * Specified by: See Section A5.2.3.
276 */
277 static inline const ClassDecoder &decode_dp_immed(
278 const Instruction insn, const Arm32DecoderState *state) {
279 if (((insn & 0x01F00000) == 0x01100000)) {
280 return state->TestImmediate_instance_;
281 }
282
283 if (((insn & 0x01F00000) == 0x01500000)) {
284 return state->Test_instance_;
285 }
286
287 if (((insn & 0x01B00000) == 0x01300000)) {
288 return state->Test_instance_;
289 }
290
291 if (((insn & 0x01E00000) == 0x01C00000)) {
292 return state->ImmediateBic_instance_;
293 }
294
295 if (((insn & 0x01E00000) == 0x01E00000)) {
296 return state->DataProc_instance_;
297 }
298
299 if (((insn & 0x01C00000) == 0x00000000)) {
300 return state->DataProc_instance_;
301 }
302
303 if (((insn & 0x00C00000) == 0x00800000)) {
304 return state->DataProc_instance_;
305 }
306
307 if (((insn & 0x01400000) == 0x00400000)) {
308 return state->DataProc_instance_;
309 }
310
311 // Catch any attempt to fall through...
312 fprintf(stderr, "TABLE IS INCOMPLETE: dp_immed could not parse %08X",insn.bits (31,0));
313 return state->Forbidden_instance_;
314 }
315
316 /*
317 * Implementation of table mult.
318 * Specified by: See Section A5.2.5.
319 */
320 static inline const ClassDecoder &decode_mult(
321 const Instruction insn, const Arm32DecoderState *state) {
322 if (((insn & 0x00F00000) == 0x00400000)) {
323 return state->LongMultiply_instance_;
324 }
325
326 if (((insn & 0x00F00000) == 0x00600000)) {
327 return state->Multiply_instance_;
328 }
329
330 if (((insn & 0x00D00000) == 0x00500000)) {
331 return state->Undefined_instance_;
332 }
333
334 if (((insn & 0x00C00000) == 0x00000000)) {
335 return state->Multiply_instance_;
336 }
337
338 if (((insn & 0x00800000) == 0x00800000)) {
339 return state->LongMultiply_instance_;
340 }
341
342 // Catch any attempt to fall through...
343 fprintf(stderr, "TABLE IS INCOMPLETE: mult could not parse %08X",insn.bits(31, 0));
344 return state->Forbidden_instance_;
345 }
346
347 /*
348 * Implementation of table sat_add_sub.
349 * Specified by: See Section A5.2.6.
350 */
351 static inline const ClassDecoder &decode_sat_add_sub(
352 const Instruction insn, const Arm32DecoderState *state) {
353 if ((true)) {
354 return state->SatAddSub_instance_;
355 }
356
357 // Catch any attempt to fall through...
358 fprintf(stderr, "TABLE IS INCOMPLETE: sat_add_sub could not parse %08X",insn.b its(31,0));
359 return state->Forbidden_instance_;
360 }
361
362 /*
363 * Implementation of table half_mult.
364 * Specified by: See Section A5.2.7.
365 */
366 static inline const ClassDecoder &decode_half_mult(
367 const Instruction insn, const Arm32DecoderState *state) {
368 if (((insn & 0x00600000) == 0x00400000)) {
369 return state->LongMultiply_instance_;
370 }
371
372 if (((insn & 0x00600000) == 0x00600000)) {
373 return state->Multiply_instance_;
374 }
375
376 if (((insn & 0x00400000) == 0x00000000)) {
377 return state->Multiply_instance_;
378 }
379
380 // Catch any attempt to fall through...
381 fprintf(stderr, "TABLE IS INCOMPLETE: half_mult could not parse %08X",insn.bit s(31,0));
382 return state->Forbidden_instance_;
383 }
384
385 /*
386 * Implementation of table extra_load_store.
387 * Specified by: See Section A5.2.8.
388 */
389 static inline const ClassDecoder &decode_extra_load_store(
390 const Instruction insn, const Arm32DecoderState *state) {
391 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00000000) ) {
392 return state->LoadDoubleR_instance_;
393 }
394
395 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00100000) ) {
396 return state->LoadRegister_instance_;
397 }
398
399 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00400000) ) {
400 return state->LoadDoubleI_instance_;
401 }
402
403 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00500000) ) {
404 return state->LoadImmediate_instance_;
405 }
406
407 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00000000) ) {
408 return state->StoreRegister_instance_;
409 }
410
411 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00100000) ) {
412 return state->LoadRegister_instance_;
413 }
414
415 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00400000) ) {
416 return state->StoreImmediate_instance_;
417 }
418
419 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00500000) ) {
420 return state->LoadImmediate_instance_;
421 }
422
423 // Catch any attempt to fall through...
424 fprintf(stderr, "TABLE IS INCOMPLETE: extra_load_store could not parse %08X",i nsn.bits(31,0));
425 return state->Forbidden_instance_;
426 }
427
428 /*
429 * Implementation of table sync.
430 * Specified by: See Section A5.2.10.
431 */
432 static inline const ClassDecoder &decode_sync(
433 const Instruction insn, const Arm32DecoderState *state) {
434 if (((insn & 0x00F00000) == 0x00800000)) {
435 return state->StoreExclusive_instance_;
436 }
437
438 if (((insn & 0x00F00000) == 0x00900000)) {
439 return state->LoadExclusive_instance_;
440 }
441
442 if (((insn & 0x00F00000) == 0x00B00000)) {
443 return state->LoadDoubleExclusive_instance_;
444 }
445
446 if (((insn & 0x00F00000) == 0x00C00000)) {
447 return state->StoreExclusive_instance_;
448 }
449
450 if (((insn & 0x00B00000) == 0x00000000)) {
451 return state->Deprecated_instance_;
452 }
453
454 if (((insn & 0x00B00000) == 0x00A00000)) {
455 return state->StoreExclusive_instance_;
456 }
457
458 if (((insn & 0x00D00000) == 0x00D00000)) {
459 return state->LoadExclusive_instance_;
460 }
461
462 if ((true)) {
463 return state->Undefined_instance_;
464 }
465
466 // Catch any attempt to fall through...
467 fprintf(stderr, "TABLE IS INCOMPLETE: sync could not parse %08X",insn.bits(31, 0));
468 return state->Forbidden_instance_;
469 }
470
471 /*
472 * Implementation of table msr_and_hints.
473 * Specified by: See Section A5.2.11.
474 */
475 static inline const ClassDecoder &decode_msr_and_hints(
476 const Instruction insn, const Arm32DecoderState *state) {
477 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000000)) {
478 return state->EffectiveNoOp_instance_;
479 }
480
481 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000002)) {
482 return state->EffectiveNoOp_instance_;
483 }
484
485 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000004)) {
486 return state->EffectiveNoOp_instance_;
487 }
488
489 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FD) == 0x00000001)) {
490 return state->EffectiveNoOp_instance_;
491 }
492
493 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000F0) == 0x000000F0)) {
494 return state->EffectiveNoOp_instance_;
495 }
496
497 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00040000) && (true)) {
498 return state->MoveToStatusRegister_instance_;
499 }
500
501 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000B0000) == 0x00080000) && (true)) {
502 return state->MoveToStatusRegister_instance_;
503 }
504
505 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00030000) == 0x00010000) && (true)) {
506 return state->Forbidden_instance_;
507 }
508
509 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00020000) == 0x00020000) && (true)) {
510 return state->Forbidden_instance_;
511 }
512
513 if (((insn & 0x00400000) == 0x00400000) && (true) && (true)) {
514 return state->Forbidden_instance_;
515 }
516
517 if ((true) && (true) && (true)) {
518 return state->Forbidden_instance_;
519 }
520
521 // Catch any attempt to fall through...
522 fprintf(stderr, "TABLE IS INCOMPLETE: msr_and_hints could not parse %08X",insn .bits(31,0));
523 return state->Forbidden_instance_;
524 }
525
526 /*
527 * Implementation of table misc.
528 * Specified by: See Section A5.2.12.
529 */
530 static inline const ClassDecoder &decode_misc(
531 const Instruction insn, const Arm32DecoderState *state) {
532 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00000000)) {
533 return state->MoveToStatusRegister_instance_;
534 }
535
536 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00010000)) {
537 return state->Forbidden_instance_;
538 }
539
540 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00020000) == 0x00020000)) {
541 return state->Forbidden_instance_;
542 }
543
544 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00600000) && (true)) {
545 return state->Forbidden_instance_;
546 }
547
548 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00200000) == 0x00000000) && (true)) {
549 return state->DataProc_instance_;
550 }
551
552 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00200000) && (true)) {
553 return state->BxBlx_instance_;
554 }
555
556 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00600000) && (true)) {
557 return state->DataProc_instance_;
558 }
559
560 if (((insn & 0x00000070) == 0x00000020) && ((insn & 0x00600000) == 0x00200000) && (true)) {
561 return state->Forbidden_instance_;
562 }
563
564 if (((insn & 0x00000070) == 0x00000030) && ((insn & 0x00600000) == 0x00200000) && (true)) {
565 return state->BxBlx_instance_;
566 }
567
568 if (((insn & 0x00000070) == 0x00000050) && (true) && (true)) {
569 return decode_sat_add_sub(insn, state);
570 }
571
572 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00200000) && (true)) {
573 return state->Breakpoint_instance_;
574 }
575
576 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00600000) && (true)) {
577 return state->Forbidden_instance_;
578 }
579
580 if ((true) && (true) && (true)) {
581 return state->Undefined_instance_;
582 }
583
584 // Catch any attempt to fall through...
585 fprintf(stderr, "TABLE IS INCOMPLETE: misc could not parse %08X",insn.bits(31, 0));
586 return state->Forbidden_instance_;
587 }
588
589 /*
590 * Implementation of table load_store_word_byte.
591 * Specified by: See Section A5.3.
592 */
593 static inline const ClassDecoder &decode_load_store_word_byte(
594 const Instruction insn, const Arm32DecoderState *state) {
595 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && (true)) {
596 return state->Forbidden_instance_;
597 }
598
599 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00000000) && (true)) {
600 return state->StoreImmediate_instance_;
601 }
602
603 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00100000) && (true)) {
604 return state->LoadImmediate_instance_;
605 }
606
607 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x00000010) == 0x00000000)) {
608 return state->Forbidden_instance_;
609 }
610
611 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
612 return state->StoreRegister_instance_;
613 }
614
615 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000010) == 0x00000000)) {
616 return state->LoadRegister_instance_;
617 }
618
619 // Catch any attempt to fall through...
620 fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08 X",insn.bits(31,0));
621 return state->Forbidden_instance_;
622 }
623
624 /*
625 * Implementation of table media.
626 * Specified by: See Section A5.4.
627 */
628 static inline const ClassDecoder &decode_media(
629 const Instruction insn, const Arm32DecoderState *state) {
630 if (((insn & 0x01F00000) == 0x01800000) && ((insn & 0x000000E0) == 0x00000000) ) {
631 return state->Multiply_instance_;
632 }
633
634 if (((insn & 0x01F00000) == 0x01F00000) && ((insn & 0x000000E0) == 0x000000E0) ) {
635 return state->Roadblock_instance_;
636 }
637
638 if (((insn & 0x01E00000) == 0x01C00000) && ((insn & 0x00000060) == 0x00000000) ) {
639 return state->DataProc_instance_;
640 }
641
642 if (((insn & 0x01A00000) == 0x01A00000) && ((insn & 0x00000060) == 0x00000040) ) {
643 return state->DataProc_instance_;
644 }
645
646 if (((insn & 0x01800000) == 0x00000000) && (true)) {
647 return decode_parallel_add_sub(insn, state);
648 }
649
650 if (((insn & 0x01800000) == 0x00800000) && (true)) {
651 return decode_pack_sat_rev(insn, state);
652 }
653
654 if (((insn & 0x01800000) == 0x01000000) && (true)) {
655 return decode_signed_mult(insn, state);
656 }
657
658 if ((true) && (true)) {
659 return state->Undefined_instance_;
660 }
661
662 // Catch any attempt to fall through...
663 fprintf(stderr, "TABLE IS INCOMPLETE: media could not parse %08X",insn.bits(31 ,0));
664 return state->Forbidden_instance_;
665 }
666
667 /*
668 * Implementation of table parallel_add_sub.
669 * Specified by: See Sections A5.4.1, A5.4.2.
670 */
671 static inline const ClassDecoder &decode_parallel_add_sub(
672 const Instruction insn, const Arm32DecoderState *state) {
673 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000080) ) {
674 return state->DataProc_instance_;
675 }
676
677 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x000000E0) ) {
678 return state->DataProc_instance_;
679 }
680
681 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x00000080) == 0x00000000) ) {
682 return state->DataProc_instance_;
683 }
684
685 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x00000080) ) {
686 return state->DataProc_instance_;
687 }
688
689 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x000000E0) ) {
690 return state->DataProc_instance_;
691 }
692
693 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000080) == 0x00000000) ) {
694 return state->DataProc_instance_;
695 }
696
697 if ((true) && (true)) {
698 return state->Undefined_instance_;
699 }
700
701 // Catch any attempt to fall through...
702 fprintf(stderr, "TABLE IS INCOMPLETE: parallel_add_sub could not parse %08X",i nsn.bits(31,0));
703 return state->Forbidden_instance_;
704 }
705
706 /*
707 * Implementation of table pack_sat_rev.
708 * Specified by: See Section A5.4.3.
709 */
710 static inline const ClassDecoder &decode_pack_sat_rev(
711 const Instruction insn, const Arm32DecoderState *state) {
712 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000E0) == 0x000000A0) ) {
713 return state->PackSatRev_instance_;
714 }
715
716 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000020) == 0x00000000) ) {
717 return state->PackSatRev_instance_;
718 }
719
720 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x000000E0) == 0x00000060) ) {
721 return state->PackSatRev_instance_;
722 }
723
724 if (((insn & 0x00700000) == 0x00600000) && ((insn & 0x000000A0) == 0x00000020) ) {
725 return state->PackSatRev_instance_;
726 }
727
728 if (((insn & 0x00700000) == 0x00700000) && ((insn & 0x000000E0) == 0x00000020) ) {
729 return state->PackSatRev_instance_;
730 }
731
732 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x00000060) ) {
733 return state->PackSatRev_instance_;
734 }
735
736 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x000000A0) ) {
737 return state->PackSatRev_instance_;
738 }
739
740 if (((insn & 0x00500000) == 0x00000000) && ((insn & 0x000000E0) == 0x00000060) ) {
741 return state->PackSatRev_instance_;
742 }
743
744 if (((insn & 0x00600000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000020) ) {
745 return state->PackSatRev_instance_;
746 }
747
748 if (((insn & 0x00200000) == 0x00200000) && ((insn & 0x00000020) == 0x00000000) ) {
749 return state->PackSatRev_instance_;
750 }
751
752 if ((true) && (true)) {
753 return state->Undefined_instance_;
754 }
755
756 // Catch any attempt to fall through...
757 fprintf(stderr, "TABLE IS INCOMPLETE: pack_sat_rev could not parse %08X",insn. bits(31,0));
758 return state->Forbidden_instance_;
759 }
760
761 /*
762 * Implementation of table signed_mult.
763 * Specified by: See Section A5.4.4.
764 */
765 static inline const ClassDecoder &decode_signed_mult(
766 const Instruction insn, const Arm32DecoderState *state) {
767 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000C0) == 0x00000040) && ((insn & 0x0000F000) != 0x0000F000)) {
768 return state->Multiply_instance_;
769 }
770
771 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
772 return state->Multiply_instance_;
773 }
774
775 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
776 return state->LongMultiply_instance_;
777 }
778
779 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x00000000) && (true)) {
780 return state->Multiply_instance_;
781 }
782
783 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x000000C0) && (true)) {
784 return state->Multiply_instance_;
785 }
786
787 if ((true) && (true) && (true)) {
788 return state->Undefined_instance_;
789 }
790
791 // Catch any attempt to fall through...
792 fprintf(stderr, "TABLE IS INCOMPLETE: signed_mult could not parse %08X",insn.b its(31,0));
793 return state->Forbidden_instance_;
794 }
795
796 /*
797 * Implementation of table branch_block_xfer.
798 * Specified by: See Section A5.5.
799 */
800 static inline const ClassDecoder &decode_branch_block_xfer(
801 const Instruction insn, const Arm32DecoderState *state) {
802 if (((insn & 0x02500000) == 0x00000000)) {
803 return state->StoreImmediate_instance_;
804 }
805
806 if (((insn & 0x02500000) == 0x00100000)) {
807 return state->LoadMultiple_instance_;
808 }
809
810 if (((insn & 0x02400000) == 0x00400000)) {
811 return state->Forbidden_instance_;
812 }
813
814 if (((insn & 0x02000000) == 0x02000000)) {
815 return state->Branch_instance_;
816 }
817
818 // Catch any attempt to fall through...
819 fprintf(stderr, "TABLE IS INCOMPLETE: branch_block_xfer could not parse %08X", insn.bits(31,0));
820 return state->Forbidden_instance_;
821 }
822
823 /*
824 * Implementation of table super_cop.
825 * Specified by: See Section A5.6.
826 */
827 static inline const ClassDecoder &decode_super_cop(
828 const Instruction insn, const Arm32DecoderState *state) {
829 if (((insn & 0x03F00000) == 0x00400000) && (true)) {
830 return state->CoprocessorOp_instance_;
831 }
832
833 if (((insn & 0x03F00000) == 0x00500000) && (true)) {
834 return state->MoveDoubleFromCoprocessor_instance_;
835 }
836
837 if (((insn & 0x03E00000) == 0x00000000) && (true)) {
838 return state->Undefined_instance_;
839 }
840
841 if (((insn & 0x03100000) == 0x02000000) && ((insn & 0x00000010) == 0x00000010) ) {
842 return state->CoprocessorOp_instance_;
843 }
844
845 if (((insn & 0x03100000) == 0x02100000) && ((insn & 0x00000010) == 0x00000010) ) {
846 return state->MoveFromCoprocessor_instance_;
847 }
848
849 if (((insn & 0x02100000) == 0x00000000) && (true)) {
850 return state->StoreCoprocessor_instance_;
851 }
852
853 if (((insn & 0x02100000) == 0x00100000) && (true)) {
854 return state->LoadCoprocessor_instance_;
855 }
856
857 if (((insn & 0x03000000) == 0x02000000) && ((insn & 0x00000010) == 0x00000000) ) {
858 return state->CoprocessorOp_instance_;
859 }
860
861 if (((insn & 0x03000000) == 0x03000000) && (true)) {
862 return state->Forbidden_instance_;
863 }
864
865 // Catch any attempt to fall through...
866 fprintf(stderr, "TABLE IS INCOMPLETE: super_cop could not parse %08X",insn.bit s(31,0));
867 return state->Forbidden_instance_;
868 }
869
870 /*
871 * Implementation of table unconditional.
872 * Specified by: See Section A5.7.
873 */
874 static inline const ClassDecoder &decode_unconditional(
875 const Instruction insn, const Arm32DecoderState *state) {
876 if (((insn & 0x0FF00000) == 0x0C400000) && (true) && (true)) {
877 return state->CoprocessorOp_instance_;
878 }
879
880 if (((insn & 0x0FF00000) == 0x0C500000) && (true) && (true)) {
881 return state->MoveDoubleFromCoprocessor_instance_;
882 }
883
884 if (((insn & 0x0FB00000) == 0x0C200000) && (true) && (true)) {
885 return state->StoreCoprocessor_instance_;
886 }
887
888 if (((insn & 0x0FB00000) == 0x0C300000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
889 return state->LoadCoprocessor_instance_;
890 }
891
892 if (((insn & 0x0F900000) == 0x0C800000) && (true) && (true)) {
893 return state->StoreCoprocessor_instance_;
894 }
895
896 if (((insn & 0x0F900000) == 0x0C900000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
897 return state->LoadCoprocessor_instance_;
898 }
899
900 if (((insn & 0x0E500000) == 0x08100000) && (true) && (true)) {
901 return state->Forbidden_instance_;
902 }
903
904 if (((insn & 0x0E500000) == 0x08400000) && (true) && (true)) {
905 return state->Forbidden_instance_;
906 }
907
908 if (((insn & 0x0F100000) == 0x0D000000) && (true) && (true)) {
909 return state->StoreCoprocessor_instance_;
910 }
911
912 if (((insn & 0x0F100000) == 0x0D100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
913 return state->LoadCoprocessor_instance_;
914 }
915
916 if (((insn & 0x0F100000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
917 return state->CoprocessorOp_instance_;
918 }
919
920 if (((insn & 0x0F100000) == 0x0E100000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
921 return state->MoveFromCoprocessor_instance_;
922 }
923
924 if (((insn & 0x0F000000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
925 return state->CoprocessorOp_instance_;
926 }
927
928 if (((insn & 0x0E000000) == 0x0A000000) && (true) && (true)) {
929 return state->Forbidden_instance_;
930 }
931
932 if (((insn & 0x08000000) == 0x00000000) && (true) && (true)) {
933 return decode_misc_hints_simd(insn, state);
934 }
935
936 if ((true) && (true) && (true)) {
937 return state->Undefined_instance_;
938 }
939
940 // Catch any attempt to fall through...
941 fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",insn .bits(31,0));
942 return state->Forbidden_instance_;
943 }
944
945 /*
946 * Implementation of table misc_hints_simd.
947 * Specified by: See Section A5.7.1.
948 */
949 static inline const ClassDecoder &decode_misc_hints_simd(
950 const Instruction insn, const Arm32DecoderState *state) {
951 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000000) && ((insn & 0x00010000) == 0x00010000)) {
952 return state->Forbidden_instance_;
953 }
954
955 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x00000020) == 0x00000000) && ((insn & 0x00010000) == 0x00000000)) {
956 return state->Forbidden_instance_;
957 }
958
959 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000010) && (true)) {
960 return state->EffectiveNoOp_instance_;
961 }
962
963 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000050) && (true)) {
964 return state->EffectiveNoOp_instance_;
965 }
966
967 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000D0) == 0x00000040) && (true)) {
968 return state->EffectiveNoOp_instance_;
969 }
970
971 if (((insn & 0x07700000) == 0x04100000) && (true) && (true)) {
972 return state->EffectiveNoOp_instance_;
973 }
974
975 if (((insn & 0x07700000) == 0x04500000) && (true) && (true)) {
976 return state->EffectiveNoOp_instance_;
977 }
978
979 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
980 return state->EffectiveNoOp_instance_;
981 }
982
983 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
984 return state->Unpredictable_instance_;
985 }
986
987 if (((insn & 0x07700000) == 0x05500000) && (true) && (true)) {
988 return state->EffectiveNoOp_instance_;
989 }
990
991 if (((insn & 0x07700000) == 0x06500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
992 return state->EffectiveNoOp_instance_;
993 }
994
995 if (((insn & 0x07700000) == 0x07500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
996 return state->EffectiveNoOp_instance_;
997 }
998
999 if (((insn & 0x06700000) == 0x06100000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1000 return state->EffectiveNoOp_instance_;
1001 }
1002
1003 if (((insn & 0x06300000) == 0x04300000) && (true) && (true)) {
1004 return state->Unpredictable_instance_;
1005 }
1006
1007 if (((insn & 0x06300000) == 0x06300000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1008 return state->Unpredictable_instance_;
1009 }
1010
1011 if (((insn & 0x07100000) == 0x04000000) && (true) && (true)) {
1012 return decode_simd_load_store(insn, state);
1013 }
1014
1015 if (((insn & 0x06000000) == 0x02000000) && (true) && (true)) {
1016 return decode_simd_dp(insn, state);
1017 }
1018
1019 if ((true) && (true) && (true)) {
1020 return state->Undefined_instance_;
1021 }
1022
1023 // Catch any attempt to fall through...
1024 fprintf(stderr, "TABLE IS INCOMPLETE: misc_hints_simd could not parse %08X",in sn.bits(31,0));
1025 return state->Forbidden_instance_;
1026 }
1027
1028 /*
1029 * Implementation of table simd_dp.
1030 * Specified by: See Section A7.4.
1031 */
1032 static inline const ClassDecoder &decode_simd_dp(
1033 const Instruction insn, const Arm32DecoderState *state) {
1034 if (((insn & 0x01000000) == 0x00000000) && ((insn & 0x00B00000) == 0x00B00000) && (true) && ((insn & 0x00000010) == 0x00000000)) {
1035 return state->EffectiveNoOp_instance_;
1036 }
1037
1038 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000F00) == 0x00000C00) && ((insn & 0x00000090) == 0x00000000)) {
1039 return state->EffectiveNoOp_instance_;
1040 }
1041
1042 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000C00) == 0x00000800) && ((insn & 0x00000010) == 0x00000000)) {
1043 return state->EffectiveNoOp_instance_;
1044 }
1045
1046 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000800) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
1047 return decode_simd_dp_2misc(insn, state);
1048 }
1049
1050 if ((true) && ((insn & 0x00B80000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1051 return decode_simd_dp_1imm(insn, state);
1052 }
1053
1054 if ((true) && ((insn & 0x00B80000) == 0x00880000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1055 return decode_simd_dp_2shift(insn, state);
1056 }
1057
1058 if ((true) && ((insn & 0x00B00000) == 0x00900000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1059 return decode_simd_dp_2shift(insn, state);
1060 }
1061
1062 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
1063 return decode_simd_dp_3diff(insn, state);
1064 }
1065
1066 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
1067 return decode_simd_dp_2scalar(insn, state);
1068 }
1069
1070 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
1071 return decode_simd_dp_3diff(insn, state);
1072 }
1073
1074 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
1075 return decode_simd_dp_2scalar(insn, state);
1076 }
1077
1078 if ((true) && ((insn & 0x00A00000) == 0x00A00000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1079 return decode_simd_dp_2shift(insn, state);
1080 }
1081
1082 if ((true) && ((insn & 0x00800000) == 0x00000000) && (true) && (true)) {
1083 return decode_simd_dp_3same(insn, state);
1084 }
1085
1086 if ((true) && ((insn & 0x00800000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000090)) {
1087 return decode_simd_dp_2shift(insn, state);
1088 }
1089
1090 if ((true) && (true) && (true) && (true)) {
1091 return state->Undefined_instance_;
1092 }
1093
1094 // Catch any attempt to fall through...
1095 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp could not parse %08X",insn.bits( 31,0));
1096 return state->Forbidden_instance_;
1097 }
1098
1099 /*
1100 * Implementation of table simd_dp_3same.
1101 * Specified by: See Section A7.4.1.
1102 */
1103 static inline const ClassDecoder &decode_simd_dp_3same(
1104 const Instruction insn, const Arm32DecoderState *state) {
1105 if (((insn & 0x00000F00) == 0x00000100) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1106 return state->EffectiveNoOp_instance_;
1107 }
1108
1109 if (((insn & 0x00000F00) == 0x00000500) && (true) && (true) && (true)) {
1110 return state->EffectiveNoOp_instance_;
1111 }
1112
1113 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1114 return state->EffectiveNoOp_instance_;
1115 }
1116
1117 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1118 return state->EffectiveNoOp_instance_;
1119 }
1120
1121 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1122 return state->EffectiveNoOp_instance_;
1123 }
1124
1125 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00000000)) {
1126 return state->EffectiveNoOp_instance_;
1127 }
1128
1129 if (((insn & 0x00000F00) == 0x00000D00) && (true) && ((insn & 0x01000000) == 0 x00000000) && (true)) {
1130 return state->EffectiveNoOp_instance_;
1131 }
1132
1133 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00200000)) {
1134 return state->EffectiveNoOp_instance_;
1135 }
1136
1137 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && (true) && ((insn & 0x00200000) == 0x00000000)) {
1138 return state->EffectiveNoOp_instance_;
1139 }
1140
1141 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1142 return state->EffectiveNoOp_instance_;
1143 }
1144
1145 if (((insn & 0x00000700) == 0x00000700) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1146 return state->EffectiveNoOp_instance_;
1147 }
1148
1149 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1150 return state->EffectiveNoOp_instance_;
1151 }
1152
1153 if (((insn & 0x00000B00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x00000000) && (true)) {
1154 return state->EffectiveNoOp_instance_;
1155 }
1156
1157 if (((insn & 0x00000D00) == 0x00000100) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1158 return state->EffectiveNoOp_instance_;
1159 }
1160
1161 if (((insn & 0x00000D00) == 0x00000800) && (true) && (true) && (true)) {
1162 return state->EffectiveNoOp_instance_;
1163 }
1164
1165 if (((insn & 0x00000900) == 0x00000000) && (true) && (true) && (true)) {
1166 return state->EffectiveNoOp_instance_;
1167 }
1168
1169 if ((true) && (true) && (true) && (true)) {
1170 return state->Undefined_instance_;
1171 }
1172
1173 // Catch any attempt to fall through...
1174 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3same could not parse %08X",insn .bits(31,0));
1175 return state->Forbidden_instance_;
1176 }
1177
1178 /*
1179 * Implementation of table simd_dp_3diff.
1180 * Specified by: See Section A7.4.2.
1181 */
1182 static inline const ClassDecoder &decode_simd_dp_3diff(
1183 const Instruction insn, const Arm32DecoderState *state) {
1184 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x01000000) == 0x00000000) ) {
1185 return state->EffectiveNoOp_instance_;
1186 }
1187
1188 if (((insn & 0x00000D00) == 0x00000900) && ((insn & 0x01000000) == 0x00000000) ) {
1189 return state->EffectiveNoOp_instance_;
1190 }
1191
1192 if (((insn & 0x00000900) == 0x00000800) && (true)) {
1193 return state->EffectiveNoOp_instance_;
1194 }
1195
1196 if (((insn & 0x00000800) == 0x00000000) && (true)) {
1197 return state->EffectiveNoOp_instance_;
1198 }
1199
1200 if ((true) && (true)) {
1201 return state->Undefined_instance_;
1202 }
1203
1204 // Catch any attempt to fall through...
1205 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3diff could not parse %08X",insn .bits(31,0));
1206 return state->Forbidden_instance_;
1207 }
1208
1209 /*
1210 * Implementation of table simd_dp_2scalar.
1211 * Specified by: See Section A7.4.3.
1212 */
1213 static inline const ClassDecoder &decode_simd_dp_2scalar(
1214 const Instruction insn, const Arm32DecoderState *state) {
1215 if (((insn & 0x00000F00) == 0x00000A00) && (true)) {
1216 return state->EffectiveNoOp_instance_;
1217 }
1218
1219 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x01000000) == 0x00000000) ) {
1220 return state->EffectiveNoOp_instance_;
1221 }
1222
1223 if (((insn & 0x00000B00) == 0x00000200) && (true)) {
1224 return state->EffectiveNoOp_instance_;
1225 }
1226
1227 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x01000000) == 0x00000000) ) {
1228 return state->EffectiveNoOp_instance_;
1229 }
1230
1231 if (((insn & 0x00000200) == 0x00000000) && (true)) {
1232 return state->EffectiveNoOp_instance_;
1233 }
1234
1235 if ((true) && (true)) {
1236 return state->Undefined_instance_;
1237 }
1238
1239 // Catch any attempt to fall through...
1240 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2scalar could not parse %08X",in sn.bits(31,0));
1241 return state->Forbidden_instance_;
1242 }
1243
1244 /*
1245 * Implementation of table simd_dp_2shift.
1246 * Specified by: See Section A7.4.4.
1247 */
1248 static inline const ClassDecoder &decode_simd_dp_2shift(
1249 const Instruction insn, const Arm32DecoderState *state) {
1250 if (((insn & 0x00000F00) == 0x00000500) && ((insn & 0x01000000) == 0x00000000) && (true) && (true)) {
1251 return state->EffectiveNoOp_instance_;
1252 }
1253
1254 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x00000040) == 0x00000000) && ((insn & 0x00000080) == 0x00000000)) {
1255 return state->EffectiveNoOp_instance_;
1256 }
1257
1258 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00000040) == 0x00000000) && (true)) {
1259 return state->EffectiveNoOp_instance_;
1260 }
1261
1262 if (((insn & 0x00000F00) == 0x00000800) && (true) && ((insn & 0x00000040) == 0 x00000040) && (true)) {
1263 return state->EffectiveNoOp_instance_;
1264 }
1265
1266 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1267 return state->EffectiveNoOp_instance_;
1268 }
1269
1270 if (((insn & 0x00000F00) == 0x00000A00) && (true) && ((insn & 0x00000040) == 0 x00000000) && (true)) {
1271 return state->EffectiveNoOp_instance_;
1272 }
1273
1274 if (((insn & 0x00000E00) == 0x00000400) && ((insn & 0x01000000) == 0x01000000) && (true) && (true)) {
1275 return state->EffectiveNoOp_instance_;
1276 }
1277
1278 if (((insn & 0x00000600) == 0x00000600) && (true) && (true) && (true)) {
1279 return state->EffectiveNoOp_instance_;
1280 }
1281
1282 if (((insn & 0x00000C00) == 0x00000000) && (true) && (true) && (true)) {
1283 return state->EffectiveNoOp_instance_;
1284 }
1285
1286 if ((true) && (true) && (true) && (true)) {
1287 return state->Undefined_instance_;
1288 }
1289
1290 // Catch any attempt to fall through...
1291 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2shift could not parse %08X",ins n.bits(31,0));
1292 return state->Forbidden_instance_;
1293 }
1294
1295 /*
1296 * Implementation of table simd_dp_2misc.
1297 * Specified by: See Section A7.4.5.
1298 */
1299 static inline const ClassDecoder &decode_simd_dp_2misc(
1300 const Instruction insn, const Arm32DecoderState *state) {
1301 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000780) == 0x00000700) ) {
1302 return state->EffectiveNoOp_instance_;
1303 }
1304
1305 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000380) == 0x00000100) ) {
1306 return state->EffectiveNoOp_instance_;
1307 }
1308
1309 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000580) == 0x00000580) ) {
1310 return state->EffectiveNoOp_instance_;
1311 }
1312
1313 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000100) == 0x00000000) ) {
1314 return state->EffectiveNoOp_instance_;
1315 }
1316
1317 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000380) == 0x00000380) ) {
1318 return state->EffectiveNoOp_instance_;
1319 }
1320
1321 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000280) == 0x00000200) ) {
1322 return state->EffectiveNoOp_instance_;
1323 }
1324
1325 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000200) == 0x00000000) ) {
1326 return state->EffectiveNoOp_instance_;
1327 }
1328
1329 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000007C0) == 0x00000300) ) {
1330 return state->EffectiveNoOp_instance_;
1331 }
1332
1333 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000006C0) == 0x00000600) ) {
1334 return state->EffectiveNoOp_instance_;
1335 }
1336
1337 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000700) == 0x00000200) ) {
1338 return state->EffectiveNoOp_instance_;
1339 }
1340
1341 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000600) == 0x00000000) ) {
1342 return state->EffectiveNoOp_instance_;
1343 }
1344
1345 if (((insn & 0x00030000) == 0x00030000) && ((insn & 0x00000400) == 0x00000400) ) {
1346 return state->EffectiveNoOp_instance_;
1347 }
1348
1349 if ((true) && (true)) {
1350 return state->Undefined_instance_;
1351 }
1352
1353 // Catch any attempt to fall through...
1354 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2misc could not parse %08X",insn .bits(31,0));
1355 return state->Forbidden_instance_;
1356 }
1357
1358 /*
1359 * Implementation of table simd_dp_1imm.
1360 * Specified by: See Section A7.4.6.
1361 */
1362 static inline const ClassDecoder &decode_simd_dp_1imm(
1363 const Instruction insn, const Arm32DecoderState *state) {
1364 if (((insn & 0x00000020) == 0x00000000) && (true)) {
1365 return state->EffectiveNoOp_instance_;
1366 }
1367
1368 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000E00) ) {
1369 return state->EffectiveNoOp_instance_;
1370 }
1371
1372 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000F00) ) {
1373 return state->Undefined_instance_;
1374 }
1375
1376 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000E00) == 0x00000C00) ) {
1377 return state->EffectiveNoOp_instance_;
1378 }
1379
1380 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000C00) == 0x00000800) ) {
1381 return state->EffectiveNoOp_instance_;
1382 }
1383
1384 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000800) == 0x00000000) ) {
1385 return state->EffectiveNoOp_instance_;
1386 }
1387
1388 // Catch any attempt to fall through...
1389 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_1imm could not parse %08X",insn. bits(31,0));
1390 return state->Forbidden_instance_;
1391 }
1392
1393 /*
1394 * Implementation of table simd_load_store.
1395 * Specified by: See Section A7.7.
1396 */
1397 static inline const ClassDecoder &decode_simd_load_store(
1398 const Instruction insn, const Arm32DecoderState *state) {
1399 if (((insn & 0x00200000) == 0x00000000)) {
1400 return decode_simd_load_store_l0(insn, state);
1401 }
1402
1403 if (((insn & 0x00200000) == 0x00200000)) {
1404 return decode_simd_load_store_l1(insn, state);
1405 }
1406
1407 // Catch any attempt to fall through...
1408 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store could not parse %08X",in sn.bits(31,0));
1409 return state->Forbidden_instance_;
1410 }
1411
1412 /*
1413 * Implementation of table simd_load_store_l0.
1414 * Specified by: See Section A7.7, Table A7-20.
1415 */
1416 static inline const ClassDecoder &decode_simd_load_store_l0(
1417 const Instruction insn, const Arm32DecoderState *state) {
1418 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1419 return state->VectorStore_instance_;
1420 }
1421
1422 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1423 return state->VectorStore_instance_;
1424 }
1425
1426 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1427 return state->VectorStore_instance_;
1428 }
1429
1430 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1431 return state->VectorStore_instance_;
1432 }
1433
1434 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000C00) == 0x00000800) ) {
1435 return state->VectorStore_instance_;
1436 }
1437
1438 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000800) == 0x00000000) ) {
1439 return state->VectorStore_instance_;
1440 }
1441
1442 if ((true) && (true)) {
1443 return state->Undefined_instance_;
1444 }
1445
1446 // Catch any attempt to fall through...
1447 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l0 could not parse %08X" ,insn.bits(31,0));
1448 return state->Forbidden_instance_;
1449 }
1450
1451 /*
1452 * Implementation of table simd_load_store_l1.
1453 * Specified by: See Section A7.7, Table A7-21.
1454 */
1455 static inline const ClassDecoder &decode_simd_load_store_l1(
1456 const Instruction insn, const Arm32DecoderState *state) {
1457 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1458 return state->VectorLoad_instance_;
1459 }
1460
1461 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1462 return state->VectorLoad_instance_;
1463 }
1464
1465 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1466 return state->VectorLoad_instance_;
1467 }
1468
1469 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1470 return state->VectorLoad_instance_;
1471 }
1472
1473 if (((insn & 0x00800000) == 0x00800000) && (true)) {
1474 return state->VectorLoad_instance_;
1475 }
1476
1477 if ((true) && (true)) {
1478 return state->Undefined_instance_;
1479 }
1480
1481 // Catch any attempt to fall through...
1482 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l1 could not parse %08X" ,insn.bits(31,0));
1483 return state->Forbidden_instance_;
1484 }
1485
1486 Arm32DecoderState::Arm32DecoderState() :
1487 DecoderState()
1488 , CoprocessorOp_instance_() 31 , CoprocessorOp_instance_()
32
33 , DataProc_instance_()
34
35 , Deprecated_instance_()
36
37 , EffectiveNoOp_instance_()
38
39 , Forbidden_instance_()
40
1489 , ImmediateBic_instance_() 41 , ImmediateBic_instance_()
42
43 , LoadCoprocessor_instance_()
44
45 , LoadDoubleExclusive_instance_()
46
47 , LoadDoubleI_instance_()
48
49 , LoadDoubleR_instance_()
50
51 , LoadExclusive_instance_()
52
53 , LoadImmediate_instance_()
54
1490 , LoadMultiple_instance_() 55 , LoadMultiple_instance_()
1491 , LoadCoprocessor_instance_() 56
1492 , LoadDoubleExclusive_instance_() 57 , LoadRegister_instance_()
1493 , Branch_instance_() 58
59 , LongMultiply_instance_()
60
61 , MoveDoubleFromCoprocessor_instance_()
62
63 , MoveFromCoprocessor_instance_()
64
65 , MoveToStatusRegister_instance_()
66
67 , Multiply_instance_()
68
69 , PackSatRev_instance_()
70
71 , Roadblock_instance_()
72
73 , SatAddSub_instance_()
74
75 , StoreCoprocessor_instance_()
76
77 , StoreExclusive_instance_()
78
79 , StoreImmediate_instance_()
80
81 , StoreRegister_instance_()
82
1494 , Test_instance_() 83 , Test_instance_()
1495 , StoreRegister_instance_() 84
1496 , MoveDoubleFromCoprocessor_instance_()
1497 , TestImmediate_instance_() 85 , TestImmediate_instance_()
1498 , BxBlx_instance_() 86
1499 , EffectiveNoOp_instance_() 87 , Unary3RegisterShiftedOp_instance_()
1500 , LongMultiply_instance_() 88
1501 , Binary4RegisterShiftedOp_instance_() 89 , Undefined_instance_()
1502 , Breakpoint_instance_() 90
1503 , Multiply_instance_() 91 , Unpredictable_instance_()
1504 , PackSatRev_instance_() 92
1505 , LoadExclusive_instance_() 93 , VectorLoad_instance_()
94
1506 , VectorStore_instance_() 95 , VectorStore_instance_()
1507 , Unary3RegisterShiftedOp_instance_() 96
1508 , Undefined_instance_() 97 {}
1509 , DataProc_instance_() 98
1510 , Deprecated_instance_() 99 Arm32DecoderState::~Arm32DecoderState() {}
1511 , LoadImmediate_instance_() 100
1512 , StoreCoprocessor_instance_() 101 // Implementation of table: ARMv7.
1513 , Roadblock_instance_() 102 // Specified by: See Section A5.1
1514 , LoadDoubleR_instance_() 103 const ClassDecoder& Arm32DecoderState::decode_ARMv7(
1515 , StoreExclusive_instance_() 104 const Instruction insn) const
1516 , StoreImmediate_instance_() 105 {
1517 , MoveFromCoprocessor_instance_() 106
1518 , LoadRegister_instance_() 107 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x04000000) && (true))
1519 , LoadDoubleI_instance_() 108
1520 , Binary3RegisterShiftedTest_instance_() 109 return decode_load_store_word_byte(insn);
1521 , Unpredictable_instance_() 110
1522 , Forbidden_instance_() 111 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000000))
1523 , VectorLoad_instance_() 112
1524 , MoveToStatusRegister_instance_() 113 return decode_load_store_word_byte(insn);
1525 , SatAddSub_instance_() 114
1526 { 115 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000010))
1527 } 116
1528 117 return decode_media(insn);
1529 Arm32DecoderState::~Arm32DecoderState() { 118
1530 } 119 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x00000000) && (true))
1531 120
1532 const ClassDecoder &Arm32DecoderState::decode(const Instruction insn) const { 121 return decode_dp_misc(insn);
1533 return decode_ARMv7(insn, this); 122
1534 } 123 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x08000000) && (true))
1535 124
1536 } // namespace 125 return decode_branch_block_xfer(insn);
126
127 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x0C000000) && (true))
128
129 return decode_super_cop(insn);
130
131 if (((insn & 0xF0000000) == 0xF0000000) && (true) && (true))
132
133 return decode_unconditional(insn);
134
135 // Catch any attempt to fall though ...
136 fprintf(stderr, "TABLE IS INCOMPLETE: ARMv7 could not parse %08X",
137 insn.bits(31, 0));
138 return Forbidden_instance_;
139 }
140
141 // Implementation of table: branch_block_xfer.
142 // Specified by: See Section A5.5
143 const ClassDecoder& Arm32DecoderState::decode_branch_block_xfer(
144 const Instruction insn) const
145 {
146 UNREFERENCED_PARAMETER(insn);
147 if (((insn & 0x02500000) == 0x00000000))
148
149 return StoreImmediate_instance_;
150
151 if (((insn & 0x02500000) == 0x00100000))
152
153 return LoadMultiple_instance_;
154
155 if (((insn & 0x02400000) == 0x00400000))
156
157 return Forbidden_instance_;
158
159 if (((insn & 0x02000000) == 0x02000000))
160
161 return Branch_instance_;
162
163 // Catch any attempt to fall though ...
164 fprintf(stderr, "TABLE IS INCOMPLETE: branch_block_xfer could not parse %08X",
165 insn.bits(31, 0));
166 return Forbidden_instance_;
167 }
168
169 // Implementation of table: dp_immed.
170 // Specified by: See Section A5.2.3
171 const ClassDecoder& Arm32DecoderState::decode_dp_immed(
172 const Instruction insn) const
173 {
174 UNREFERENCED_PARAMETER(insn);
175 if (((insn & 0x01F00000) == 0x01100000))
176
177 return TestImmediate_instance_;
178
179 if (((insn & 0x01F00000) == 0x01500000))
180
181 return Test_instance_;
182
183 if (((insn & 0x01B00000) == 0x01300000))
184
185 return Test_instance_;
186
187 if (((insn & 0x01E00000) == 0x01C00000))
188
189 return ImmediateBic_instance_;
190
191 if (((insn & 0x01E00000) == 0x01E00000))
192
193 return DataProc_instance_;
194
195 if (((insn & 0x01C00000) == 0x00000000))
196
197 return DataProc_instance_;
198
199 if (((insn & 0x00C00000) == 0x00800000))
200
201 return DataProc_instance_;
202
203 if (((insn & 0x01400000) == 0x00400000))
204
205 return DataProc_instance_;
206
207 // Catch any attempt to fall though ...
208 fprintf(stderr, "TABLE IS INCOMPLETE: dp_immed could not parse %08X",
209 insn.bits(31, 0));
210 return Forbidden_instance_;
211 }
212
213 // Implementation of table: dp_misc.
214 // Specified by: See Section A5.2
215 const ClassDecoder& Arm32DecoderState::decode_dp_misc(
216 const Instruction insn) const
217 {
218
219 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000090) == 0x00000010))
220
221 return decode_dp_reg_shifted(insn);
222
223 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000010) == 0x00000000))
224
225 return decode_dp_reg(insn);
226
227 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000090) == 0x00000080))
228
229 return decode_half_mult(insn);
230
231 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000080) == 0x00000000))
232
233 return decode_misc(insn);
234
235 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000F0) == 0x000000B0))
236
237 return decode_extra_load_store(insn);
238
239 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000D0) == 0x000000D0))
240
241 return decode_extra_load_store(insn);
242
243 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000F0) == 0x000000B0))
244
245 return Forbidden_instance_;
246
247 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000D0) == 0x000000D0))
248
249 return Forbidden_instance_;
250
251 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x000000F0) == 0x00000090))
252
253 return decode_mult(insn);
254
255 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000090))
256
257 return decode_sync(insn);
258
259 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01000000) && (true))
260
261 return DataProc_instance_;
262
263 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01200000) && (true))
264
265 return decode_msr_and_hints(insn);
266
267 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01900000) != 0x01000000) && (true))
268
269 return decode_dp_immed(insn);
270
271 // Catch any attempt to fall though ...
272 fprintf(stderr, "TABLE IS INCOMPLETE: dp_misc could not parse %08X",
273 insn.bits(31, 0));
274 return Forbidden_instance_;
275 }
276
277 // Implementation of table: dp_reg.
278 // Specified by: See Section A5.2.1
279 const ClassDecoder& Arm32DecoderState::decode_dp_reg(
280 const Instruction insn) const
281 {
282 UNREFERENCED_PARAMETER(insn);
283 if (((insn & 0x01900000) == 0x01100000))
284
285 return Test_instance_;
286
287 if (((insn & 0x01800000) == 0x01800000))
288
289 return DataProc_instance_;
290
291 if (((insn & 0x01000000) == 0x00000000))
292
293 return DataProc_instance_;
294
295 // Catch any attempt to fall though ...
296 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",
297 insn.bits(31, 0));
298 return Forbidden_instance_;
299 }
300
301 // Implementation of table: dp_reg_shifted.
302 // Specified by: See Section A5.2.2
303 const ClassDecoder& Arm32DecoderState::decode_dp_reg_shifted(
304 const Instruction insn) const
305 {
306 UNREFERENCED_PARAMETER(insn);
307 if (((insn & 0x01E00000) == 0x01A00000))
308
309 return DataProc_instance_;
310
311 if (((insn & 0x01E00000) == 0x01E00000))
312
313 return Unary3RegisterShiftedOp_instance_;
314
315 if (((insn & 0x01900000) == 0x01100000))
316
317 return Binary3RegisterShiftedTest_instance_;
318
319 if (((insn & 0x01A00000) == 0x01800000))
320
321 return Binary4RegisterShiftedOp_instance_;
322
323 if (((insn & 0x01000000) == 0x00000000))
324
325 return Binary4RegisterShiftedOp_instance_;
326
327 // Catch any attempt to fall though ...
328 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg_shifted could not parse %08X",
329 insn.bits(31, 0));
330 return Forbidden_instance_;
331 }
332
333 // Implementation of table: extra_load_store.
334 // Specified by: See Section A5.2.8
335 const ClassDecoder& Arm32DecoderState::decode_extra_load_store(
336 const Instruction insn) const
337 {
338 UNREFERENCED_PARAMETER(insn);
339 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00000000) )
340
341 return LoadDoubleR_instance_;
342
343 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00100000) )
344
345 return LoadRegister_instance_;
346
347 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00400000) )
348
349 return LoadDoubleI_instance_;
350
351 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00500000) )
352
353 return LoadImmediate_instance_;
354
355 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00000000) )
356
357 return StoreRegister_instance_;
358
359 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00100000) )
360
361 return LoadRegister_instance_;
362
363 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00400000) )
364
365 return StoreImmediate_instance_;
366
367 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00500000) )
368
369 return LoadImmediate_instance_;
370
371 // Catch any attempt to fall though ...
372 fprintf(stderr, "TABLE IS INCOMPLETE: extra_load_store could not parse %08X",
373 insn.bits(31, 0));
374 return Forbidden_instance_;
375 }
376
377 // Implementation of table: half_mult.
378 // Specified by: See Section A5.2.7
379 const ClassDecoder& Arm32DecoderState::decode_half_mult(
380 const Instruction insn) const
381 {
382 UNREFERENCED_PARAMETER(insn);
383 if (((insn & 0x00600000) == 0x00400000))
384
385 return LongMultiply_instance_;
386
387 if (((insn & 0x00600000) == 0x00600000))
388
389 return Multiply_instance_;
390
391 if (((insn & 0x00400000) == 0x00000000))
392
393 return Multiply_instance_;
394
395 // Catch any attempt to fall though ...
396 fprintf(stderr, "TABLE IS INCOMPLETE: half_mult could not parse %08X",
397 insn.bits(31, 0));
398 return Forbidden_instance_;
399 }
400
401 // Implementation of table: load_store_word_byte.
402 // Specified by: See Section A5.3
403 const ClassDecoder& Arm32DecoderState::decode_load_store_word_byte(
404 const Instruction insn) const
405 {
406 UNREFERENCED_PARAMETER(insn);
407 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && (true))
408
409 return Forbidden_instance_;
410
411 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00000000) && (true))
412
413 return StoreImmediate_instance_;
414
415 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00100000) && (true))
416
417 return LoadImmediate_instance_;
418
419 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x00000010) == 0x00000000))
420
421 return Forbidden_instance_;
422
423 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00000000) && ((insn & 0x00000010) == 0x00000000))
424
425 return StoreRegister_instance_;
426
427 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000010) == 0x00000000))
428
429 return LoadRegister_instance_;
430
431 // Catch any attempt to fall though ...
432 fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08 X",
433 insn.bits(31, 0));
434 return Forbidden_instance_;
435 }
436
437 // Implementation of table: media.
438 // Specified by: See Section A5.4
439 const ClassDecoder& Arm32DecoderState::decode_media(
440 const Instruction insn) const
441 {
442
443 if (((insn & 0x01F00000) == 0x01800000) && ((insn & 0x000000E0) == 0x00000000) )
444
445 return Multiply_instance_;
446
447 if (((insn & 0x01F00000) == 0x01F00000) && ((insn & 0x000000E0) == 0x000000E0) )
448
449 return Roadblock_instance_;
450
451 if (((insn & 0x01E00000) == 0x01C00000) && ((insn & 0x00000060) == 0x00000000) )
452
453 return DataProc_instance_;
454
455 if (((insn & 0x01A00000) == 0x01A00000) && ((insn & 0x00000060) == 0x00000040) )
456
457 return DataProc_instance_;
458
459 if (((insn & 0x01800000) == 0x00000000) && (true))
460
461 return decode_parallel_add_sub(insn);
462
463 if (((insn & 0x01800000) == 0x00800000) && (true))
464
465 return decode_pack_sat_rev(insn);
466
467 if (((insn & 0x01800000) == 0x01000000) && (true))
468
469 return decode_signed_mult(insn);
470
471 if ((true) && (true))
472
473 return Undefined_instance_;
474
475 // Catch any attempt to fall though ...
476 fprintf(stderr, "TABLE IS INCOMPLETE: media could not parse %08X",
477 insn.bits(31, 0));
478 return Forbidden_instance_;
479 }
480
481 // Implementation of table: misc.
482 // Specified by: See Section A5.2.12
483 const ClassDecoder& Arm32DecoderState::decode_misc(
484 const Instruction insn) const
485 {
486
487 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00000000))
488
489 return MoveToStatusRegister_instance_;
490
491 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00010000))
492
493 return Forbidden_instance_;
494
495 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00020000) == 0x00020000))
496
497 return Forbidden_instance_;
498
499 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00600000) && (true))
500
501 return Forbidden_instance_;
502
503 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00200000) == 0x00000000) && (true))
504
505 return DataProc_instance_;
506
507 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00200000) && (true))
508
509 return BxBlx_instance_;
510
511 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00600000) && (true))
512
513 return DataProc_instance_;
514
515 if (((insn & 0x00000070) == 0x00000020) && ((insn & 0x00600000) == 0x00200000) && (true))
516
517 return Forbidden_instance_;
518
519 if (((insn & 0x00000070) == 0x00000030) && ((insn & 0x00600000) == 0x00200000) && (true))
520
521 return BxBlx_instance_;
522
523 if (((insn & 0x00000070) == 0x00000050) && (true) && (true))
524
525 return decode_sat_add_sub(insn);
526
527 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00200000) && (true))
528
529 return Breakpoint_instance_;
530
531 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00600000) && (true))
532
533 return Forbidden_instance_;
534
535 if ((true) && (true) && (true))
536
537 return Undefined_instance_;
538
539 // Catch any attempt to fall though ...
540 fprintf(stderr, "TABLE IS INCOMPLETE: misc could not parse %08X",
541 insn.bits(31, 0));
542 return Forbidden_instance_;
543 }
544
545 // Implementation of table: misc_hints_simd.
546 // Specified by: See Section A5.7.1
547 const ClassDecoder& Arm32DecoderState::decode_misc_hints_simd(
548 const Instruction insn) const
549 {
550
551 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000000) && ((insn & 0x00010000) == 0x00010000))
552
553 return Forbidden_instance_;
554
555 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x00000020) == 0x00000000) && ((insn & 0x00010000) == 0x00000000))
556
557 return Forbidden_instance_;
558
559 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000010) && (true))
560
561 return EffectiveNoOp_instance_;
562
563 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000050) && (true))
564
565 return EffectiveNoOp_instance_;
566
567 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000D0) == 0x00000040) && (true))
568
569 return EffectiveNoOp_instance_;
570
571 if (((insn & 0x07700000) == 0x04100000) && (true) && (true))
572
573 return EffectiveNoOp_instance_;
574
575 if (((insn & 0x07700000) == 0x04500000) && (true) && (true))
576
577 return EffectiveNoOp_instance_;
578
579 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) != 0 x000F0000))
580
581 return EffectiveNoOp_instance_;
582
583 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000))
584
585 return Unpredictable_instance_;
586
587 if (((insn & 0x07700000) == 0x05500000) && (true) && (true))
588
589 return EffectiveNoOp_instance_;
590
591 if (((insn & 0x07700000) == 0x06500000) && ((insn & 0x00000010) == 0x00000000) && (true))
592
593 return EffectiveNoOp_instance_;
594
595 if (((insn & 0x07700000) == 0x07500000) && ((insn & 0x00000010) == 0x00000000) && (true))
596
597 return EffectiveNoOp_instance_;
598
599 if (((insn & 0x06700000) == 0x06100000) && ((insn & 0x00000010) == 0x00000000) && (true))
600
601 return EffectiveNoOp_instance_;
602
603 if (((insn & 0x06300000) == 0x04300000) && (true) && (true))
604
605 return Unpredictable_instance_;
606
607 if (((insn & 0x06300000) == 0x06300000) && ((insn & 0x00000010) == 0x00000000) && (true))
608
609 return Unpredictable_instance_;
610
611 if (((insn & 0x07100000) == 0x04000000) && (true) && (true))
612
613 return decode_simd_load_store(insn);
614
615 if (((insn & 0x06000000) == 0x02000000) && (true) && (true))
616
617 return decode_simd_dp(insn);
618
619 if ((true) && (true) && (true))
620
621 return Undefined_instance_;
622
623 // Catch any attempt to fall though ...
624 fprintf(stderr, "TABLE IS INCOMPLETE: misc_hints_simd could not parse %08X",
625 insn.bits(31, 0));
626 return Forbidden_instance_;
627 }
628
629 // Implementation of table: msr_and_hints.
630 // Specified by: See Section A5.2.11
631 const ClassDecoder& Arm32DecoderState::decode_msr_and_hints(
632 const Instruction insn) const
633 {
634 UNREFERENCED_PARAMETER(insn);
635 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000000))
636
637 return EffectiveNoOp_instance_;
638
639 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000002))
640
641 return EffectiveNoOp_instance_;
642
643 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000004))
644
645 return EffectiveNoOp_instance_;
646
647 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FD) == 0x00000001))
648
649 return EffectiveNoOp_instance_;
650
651 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000F0) == 0x000000F0))
652
653 return EffectiveNoOp_instance_;
654
655 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00040000) && (true))
656
657 return MoveToStatusRegister_instance_;
658
659 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000B0000) == 0x00080000) && (true))
660
661 return MoveToStatusRegister_instance_;
662
663 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00030000) == 0x00010000) && (true))
664
665 return Forbidden_instance_;
666
667 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00020000) == 0x00020000) && (true))
668
669 return Forbidden_instance_;
670
671 if (((insn & 0x00400000) == 0x00400000) && (true) && (true))
672
673 return Forbidden_instance_;
674
675 if ((true) && (true) && (true))
676
677 return Forbidden_instance_;
678
679 // Catch any attempt to fall though ...
680 fprintf(stderr, "TABLE IS INCOMPLETE: msr_and_hints could not parse %08X",
681 insn.bits(31, 0));
682 return Forbidden_instance_;
683 }
684
685 // Implementation of table: mult.
686 // Specified by: See Section A5.2.5
687 const ClassDecoder& Arm32DecoderState::decode_mult(
688 const Instruction insn) const
689 {
690 UNREFERENCED_PARAMETER(insn);
691 if (((insn & 0x00F00000) == 0x00400000))
692
693 return LongMultiply_instance_;
694
695 if (((insn & 0x00F00000) == 0x00600000))
696
697 return Multiply_instance_;
698
699 if (((insn & 0x00D00000) == 0x00500000))
700
701 return Undefined_instance_;
702
703 if (((insn & 0x00C00000) == 0x00000000))
704
705 return Multiply_instance_;
706
707 if (((insn & 0x00800000) == 0x00800000))
708
709 return LongMultiply_instance_;
710
711 // Catch any attempt to fall though ...
712 fprintf(stderr, "TABLE IS INCOMPLETE: mult could not parse %08X",
713 insn.bits(31, 0));
714 return Forbidden_instance_;
715 }
716
717 // Implementation of table: pack_sat_rev.
718 // Specified by: See Section A5.4.3
719 const ClassDecoder& Arm32DecoderState::decode_pack_sat_rev(
720 const Instruction insn) const
721 {
722 UNREFERENCED_PARAMETER(insn);
723 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000E0) == 0x000000A0) )
724
725 return PackSatRev_instance_;
726
727 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000020) == 0x00000000) )
728
729 return PackSatRev_instance_;
730
731 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x000000E0) == 0x00000060) )
732
733 return PackSatRev_instance_;
734
735 if (((insn & 0x00700000) == 0x00600000) && ((insn & 0x000000A0) == 0x00000020) )
736
737 return PackSatRev_instance_;
738
739 if (((insn & 0x00700000) == 0x00700000) && ((insn & 0x000000E0) == 0x00000020) )
740
741 return PackSatRev_instance_;
742
743 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x00000060) )
744
745 return PackSatRev_instance_;
746
747 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x000000A0) )
748
749 return PackSatRev_instance_;
750
751 if (((insn & 0x00500000) == 0x00000000) && ((insn & 0x000000E0) == 0x00000060) )
752
753 return PackSatRev_instance_;
754
755 if (((insn & 0x00600000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000020) )
756
757 return PackSatRev_instance_;
758
759 if (((insn & 0x00200000) == 0x00200000) && ((insn & 0x00000020) == 0x00000000) )
760
761 return PackSatRev_instance_;
762
763 if ((true) && (true))
764
765 return Undefined_instance_;
766
767 // Catch any attempt to fall though ...
768 fprintf(stderr, "TABLE IS INCOMPLETE: pack_sat_rev could not parse %08X",
769 insn.bits(31, 0));
770 return Forbidden_instance_;
771 }
772
773 // Implementation of table: parallel_add_sub.
774 // Specified by: See Sections A5.4.1, A5.4.2
775 const ClassDecoder& Arm32DecoderState::decode_parallel_add_sub(
776 const Instruction insn) const
777 {
778 UNREFERENCED_PARAMETER(insn);
779 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000080) )
780
781 return DataProc_instance_;
782
783 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x000000E0) )
784
785 return DataProc_instance_;
786
787 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x00000080) == 0x00000000) )
788
789 return DataProc_instance_;
790
791 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x00000080) )
792
793 return DataProc_instance_;
794
795 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x000000E0) )
796
797 return DataProc_instance_;
798
799 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000080) == 0x00000000) )
800
801 return DataProc_instance_;
802
803 if ((true) && (true))
804
805 return Undefined_instance_;
806
807 // Catch any attempt to fall though ...
808 fprintf(stderr, "TABLE IS INCOMPLETE: parallel_add_sub could not parse %08X",
809 insn.bits(31, 0));
810 return Forbidden_instance_;
811 }
812
813 // Implementation of table: sat_add_sub.
814 // Specified by: See Section A5.2.6
815 const ClassDecoder& Arm32DecoderState::decode_sat_add_sub(
816 const Instruction insn) const
817 {
818 UNREFERENCED_PARAMETER(insn);
819 if ((true))
820
821 return SatAddSub_instance_;
822
823 // Catch any attempt to fall though ...
824 fprintf(stderr, "TABLE IS INCOMPLETE: sat_add_sub could not parse %08X",
825 insn.bits(31, 0));
826 return Forbidden_instance_;
827 }
828
829 // Implementation of table: signed_mult.
830 // Specified by: See Section A5.4.4
831 const ClassDecoder& Arm32DecoderState::decode_signed_mult(
832 const Instruction insn) const
833 {
834 UNREFERENCED_PARAMETER(insn);
835 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000C0) == 0x00000040) && ((insn & 0x0000F000) != 0x0000F000))
836
837 return Multiply_instance_;
838
839 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000080) == 0x00000000) && (true))
840
841 return Multiply_instance_;
842
843 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x00000080) == 0x00000000) && (true))
844
845 return LongMultiply_instance_;
846
847 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x00000000) && (true))
848
849 return Multiply_instance_;
850
851 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x000000C0) && (true))
852
853 return Multiply_instance_;
854
855 if ((true) && (true) && (true))
856
857 return Undefined_instance_;
858
859 // Catch any attempt to fall though ...
860 fprintf(stderr, "TABLE IS INCOMPLETE: signed_mult could not parse %08X",
861 insn.bits(31, 0));
862 return Forbidden_instance_;
863 }
864
865 // Implementation of table: simd_dp.
866 // Specified by: See Section A7.4
867 const ClassDecoder& Arm32DecoderState::decode_simd_dp(
868 const Instruction insn) const
869 {
870
871 if (((insn & 0x01000000) == 0x00000000) && ((insn & 0x00B00000) == 0x00B00000) && (true) && ((insn & 0x00000010) == 0x00000000))
872
873 return EffectiveNoOp_instance_;
874
875 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000F00) == 0x00000C00) && ((insn & 0x00000090) == 0x00000000))
876
877 return EffectiveNoOp_instance_;
878
879 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000C00) == 0x00000800) && ((insn & 0x00000010) == 0x00000000))
880
881 return EffectiveNoOp_instance_;
882
883 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000800) == 0x00000000) && ((insn & 0x00000010) == 0x00000000))
884
885 return decode_simd_dp_2misc(insn);
886
887 if ((true) && ((insn & 0x00B80000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000010))
888
889 return decode_simd_dp_1imm(insn);
890
891 if ((true) && ((insn & 0x00B80000) == 0x00880000) && (true) && ((insn & 0x0000 0090) == 0x00000010))
892
893 return decode_simd_dp_2shift(insn);
894
895 if ((true) && ((insn & 0x00B00000) == 0x00900000) && (true) && ((insn & 0x0000 0090) == 0x00000010))
896
897 return decode_simd_dp_2shift(insn);
898
899 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000000))
900
901 return decode_simd_dp_3diff(insn);
902
903 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000040))
904
905 return decode_simd_dp_2scalar(insn);
906
907 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000000))
908
909 return decode_simd_dp_3diff(insn);
910
911 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000040))
912
913 return decode_simd_dp_2scalar(insn);
914
915 if ((true) && ((insn & 0x00A00000) == 0x00A00000) && (true) && ((insn & 0x0000 0090) == 0x00000010))
916
917 return decode_simd_dp_2shift(insn);
918
919 if ((true) && ((insn & 0x00800000) == 0x00000000) && (true) && (true))
920
921 return decode_simd_dp_3same(insn);
922
923 if ((true) && ((insn & 0x00800000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000090))
924
925 return decode_simd_dp_2shift(insn);
926
927 if ((true) && (true) && (true) && (true))
928
929 return Undefined_instance_;
930
931 // Catch any attempt to fall though ...
932 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp could not parse %08X",
933 insn.bits(31, 0));
934 return Forbidden_instance_;
935 }
936
937 // Implementation of table: simd_dp_1imm.
938 // Specified by: See Section A7.4.6
939 const ClassDecoder& Arm32DecoderState::decode_simd_dp_1imm(
940 const Instruction insn) const
941 {
942 UNREFERENCED_PARAMETER(insn);
943 if (((insn & 0x00000020) == 0x00000000) && (true))
944
945 return EffectiveNoOp_instance_;
946
947 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000E00) )
948
949 return EffectiveNoOp_instance_;
950
951 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000F00) )
952
953 return Undefined_instance_;
954
955 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000E00) == 0x00000C00) )
956
957 return EffectiveNoOp_instance_;
958
959 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000C00) == 0x00000800) )
960
961 return EffectiveNoOp_instance_;
962
963 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000800) == 0x00000000) )
964
965 return EffectiveNoOp_instance_;
966
967 // Catch any attempt to fall though ...
968 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_1imm could not parse %08X",
969 insn.bits(31, 0));
970 return Forbidden_instance_;
971 }
972
973 // Implementation of table: simd_dp_2misc.
974 // Specified by: See Section A7.4.5
975 const ClassDecoder& Arm32DecoderState::decode_simd_dp_2misc(
976 const Instruction insn) const
977 {
978 UNREFERENCED_PARAMETER(insn);
979 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000780) == 0x00000700) )
980
981 return EffectiveNoOp_instance_;
982
983 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000380) == 0x00000100) )
984
985 return EffectiveNoOp_instance_;
986
987 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000580) == 0x00000580) )
988
989 return EffectiveNoOp_instance_;
990
991 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000100) == 0x00000000) )
992
993 return EffectiveNoOp_instance_;
994
995 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000380) == 0x00000380) )
996
997 return EffectiveNoOp_instance_;
998
999 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000280) == 0x00000200) )
1000
1001 return EffectiveNoOp_instance_;
1002
1003 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000200) == 0x00000000) )
1004
1005 return EffectiveNoOp_instance_;
1006
1007 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000007C0) == 0x00000300) )
1008
1009 return EffectiveNoOp_instance_;
1010
1011 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000006C0) == 0x00000600) )
1012
1013 return EffectiveNoOp_instance_;
1014
1015 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000700) == 0x00000200) )
1016
1017 return EffectiveNoOp_instance_;
1018
1019 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000600) == 0x00000000) )
1020
1021 return EffectiveNoOp_instance_;
1022
1023 if (((insn & 0x00030000) == 0x00030000) && ((insn & 0x00000400) == 0x00000400) )
1024
1025 return EffectiveNoOp_instance_;
1026
1027 if ((true) && (true))
1028
1029 return Undefined_instance_;
1030
1031 // Catch any attempt to fall though ...
1032 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2misc could not parse %08X",
1033 insn.bits(31, 0));
1034 return Forbidden_instance_;
1035 }
1036
1037 // Implementation of table: simd_dp_2scalar.
1038 // Specified by: See Section A7.4.3
1039 const ClassDecoder& Arm32DecoderState::decode_simd_dp_2scalar(
1040 const Instruction insn) const
1041 {
1042 UNREFERENCED_PARAMETER(insn);
1043 if (((insn & 0x00000F00) == 0x00000A00) && (true))
1044
1045 return EffectiveNoOp_instance_;
1046
1047 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x01000000) == 0x00000000) )
1048
1049 return EffectiveNoOp_instance_;
1050
1051 if (((insn & 0x00000B00) == 0x00000200) && (true))
1052
1053 return EffectiveNoOp_instance_;
1054
1055 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x01000000) == 0x00000000) )
1056
1057 return EffectiveNoOp_instance_;
1058
1059 if (((insn & 0x00000200) == 0x00000000) && (true))
1060
1061 return EffectiveNoOp_instance_;
1062
1063 if ((true) && (true))
1064
1065 return Undefined_instance_;
1066
1067 // Catch any attempt to fall though ...
1068 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2scalar could not parse %08X",
1069 insn.bits(31, 0));
1070 return Forbidden_instance_;
1071 }
1072
1073 // Implementation of table: simd_dp_2shift.
1074 // Specified by: See Section A7.4.4
1075 const ClassDecoder& Arm32DecoderState::decode_simd_dp_2shift(
1076 const Instruction insn) const
1077 {
1078 UNREFERENCED_PARAMETER(insn);
1079 if (((insn & 0x00000F00) == 0x00000500) && ((insn & 0x01000000) == 0x00000000) && (true) && (true))
1080
1081 return EffectiveNoOp_instance_;
1082
1083 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x00000040) == 0x00000000) && ((insn & 0x00000080) == 0x00000000))
1084
1085 return EffectiveNoOp_instance_;
1086
1087 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00000040) == 0x00000000) && (true))
1088
1089 return EffectiveNoOp_instance_;
1090
1091 if (((insn & 0x00000F00) == 0x00000800) && (true) && ((insn & 0x00000040) == 0 x00000040) && (true))
1092
1093 return EffectiveNoOp_instance_;
1094
1095 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true))
1096
1097 return EffectiveNoOp_instance_;
1098
1099 if (((insn & 0x00000F00) == 0x00000A00) && (true) && ((insn & 0x00000040) == 0 x00000000) && (true))
1100
1101 return EffectiveNoOp_instance_;
1102
1103 if (((insn & 0x00000E00) == 0x00000400) && ((insn & 0x01000000) == 0x01000000) && (true) && (true))
1104
1105 return EffectiveNoOp_instance_;
1106
1107 if (((insn & 0x00000600) == 0x00000600) && (true) && (true) && (true))
1108
1109 return EffectiveNoOp_instance_;
1110
1111 if (((insn & 0x00000C00) == 0x00000000) && (true) && (true) && (true))
1112
1113 return EffectiveNoOp_instance_;
1114
1115 if ((true) && (true) && (true) && (true))
1116
1117 return Undefined_instance_;
1118
1119 // Catch any attempt to fall though ...
1120 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2shift could not parse %08X",
1121 insn.bits(31, 0));
1122 return Forbidden_instance_;
1123 }
1124
1125 // Implementation of table: simd_dp_3diff.
1126 // Specified by: See Section A7.4.2
1127 const ClassDecoder& Arm32DecoderState::decode_simd_dp_3diff(
1128 const Instruction insn) const
1129 {
1130 UNREFERENCED_PARAMETER(insn);
1131 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x01000000) == 0x00000000) )
1132
1133 return EffectiveNoOp_instance_;
1134
1135 if (((insn & 0x00000D00) == 0x00000900) && ((insn & 0x01000000) == 0x00000000) )
1136
1137 return EffectiveNoOp_instance_;
1138
1139 if (((insn & 0x00000900) == 0x00000800) && (true))
1140
1141 return EffectiveNoOp_instance_;
1142
1143 if (((insn & 0x00000800) == 0x00000000) && (true))
1144
1145 return EffectiveNoOp_instance_;
1146
1147 if ((true) && (true))
1148
1149 return Undefined_instance_;
1150
1151 // Catch any attempt to fall though ...
1152 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3diff could not parse %08X",
1153 insn.bits(31, 0));
1154 return Forbidden_instance_;
1155 }
1156
1157 // Implementation of table: simd_dp_3same.
1158 // Specified by: See Section A7.4.1
1159 const ClassDecoder& Arm32DecoderState::decode_simd_dp_3same(
1160 const Instruction insn) const
1161 {
1162 UNREFERENCED_PARAMETER(insn);
1163 if (((insn & 0x00000F00) == 0x00000100) && ((insn & 0x00000010) == 0x00000010) && (true) && (true))
1164
1165 return EffectiveNoOp_instance_;
1166
1167 if (((insn & 0x00000F00) == 0x00000500) && (true) && (true) && (true))
1168
1169 return EffectiveNoOp_instance_;
1170
1171 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true))
1172
1173 return EffectiveNoOp_instance_;
1174
1175 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000000) && (true) && (true))
1176
1177 return EffectiveNoOp_instance_;
1178
1179 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && (true))
1180
1181 return EffectiveNoOp_instance_;
1182
1183 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00000000))
1184
1185 return EffectiveNoOp_instance_;
1186
1187 if (((insn & 0x00000F00) == 0x00000D00) && (true) && ((insn & 0x01000000) == 0 x00000000) && (true))
1188
1189 return EffectiveNoOp_instance_;
1190
1191 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00200000))
1192
1193 return EffectiveNoOp_instance_;
1194
1195 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && (true) && ((insn & 0x00200000) == 0x00000000))
1196
1197 return EffectiveNoOp_instance_;
1198
1199 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && (true))
1200
1201 return EffectiveNoOp_instance_;
1202
1203 if (((insn & 0x00000700) == 0x00000700) && ((insn & 0x00000010) == 0x00000000) && (true) && (true))
1204
1205 return EffectiveNoOp_instance_;
1206
1207 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x00000010) == 0x00000010) && (true) && (true))
1208
1209 return EffectiveNoOp_instance_;
1210
1211 if (((insn & 0x00000B00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x00000000) && (true))
1212
1213 return EffectiveNoOp_instance_;
1214
1215 if (((insn & 0x00000D00) == 0x00000100) && ((insn & 0x00000010) == 0x00000000) && (true) && (true))
1216
1217 return EffectiveNoOp_instance_;
1218
1219 if (((insn & 0x00000D00) == 0x00000800) && (true) && (true) && (true))
1220
1221 return EffectiveNoOp_instance_;
1222
1223 if (((insn & 0x00000900) == 0x00000000) && (true) && (true) && (true))
1224
1225 return EffectiveNoOp_instance_;
1226
1227 if ((true) && (true) && (true) && (true))
1228
1229 return Undefined_instance_;
1230
1231 // Catch any attempt to fall though ...
1232 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3same could not parse %08X",
1233 insn.bits(31, 0));
1234 return Forbidden_instance_;
1235 }
1236
1237 // Implementation of table: simd_load_store.
1238 // Specified by: See Section A7.7
1239 const ClassDecoder& Arm32DecoderState::decode_simd_load_store(
1240 const Instruction insn) const
1241 {
1242
1243 if (((insn & 0x00200000) == 0x00000000))
1244
1245 return decode_simd_load_store_l0(insn);
1246
1247 if (((insn & 0x00200000) == 0x00200000))
1248
1249 return decode_simd_load_store_l1(insn);
1250
1251 // Catch any attempt to fall though ...
1252 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store could not parse %08X",
1253 insn.bits(31, 0));
1254 return Forbidden_instance_;
1255 }
1256
1257 // Implementation of table: simd_load_store_l0.
1258 // Specified by: See Section A7.7, Table A7 - 20
1259 const ClassDecoder& Arm32DecoderState::decode_simd_load_store_l0(
1260 const Instruction insn) const
1261 {
1262 UNREFERENCED_PARAMETER(insn);
1263 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) )
1264
1265 return VectorStore_instance_;
1266
1267 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) )
1268
1269 return VectorStore_instance_;
1270
1271 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) )
1272
1273 return VectorStore_instance_;
1274
1275 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) )
1276
1277 return VectorStore_instance_;
1278
1279 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000C00) == 0x00000800) )
1280
1281 return VectorStore_instance_;
1282
1283 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000800) == 0x00000000) )
1284
1285 return VectorStore_instance_;
1286
1287 if ((true) && (true))
1288
1289 return Undefined_instance_;
1290
1291 // Catch any attempt to fall though ...
1292 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l0 could not parse %08X" ,
1293 insn.bits(31, 0));
1294 return Forbidden_instance_;
1295 }
1296
1297 // Implementation of table: simd_load_store_l1.
1298 // Specified by: See Section A7.7, Table A7 - 21
1299 const ClassDecoder& Arm32DecoderState::decode_simd_load_store_l1(
1300 const Instruction insn) const
1301 {
1302 UNREFERENCED_PARAMETER(insn);
1303 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) )
1304
1305 return VectorLoad_instance_;
1306
1307 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) )
1308
1309 return VectorLoad_instance_;
1310
1311 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) )
1312
1313 return VectorLoad_instance_;
1314
1315 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) )
1316
1317 return VectorLoad_instance_;
1318
1319 if (((insn & 0x00800000) == 0x00800000) && (true))
1320
1321 return VectorLoad_instance_;
1322
1323 if ((true) && (true))
1324
1325 return Undefined_instance_;
1326
1327 // Catch any attempt to fall though ...
1328 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l1 could not parse %08X" ,
1329 insn.bits(31, 0));
1330 return Forbidden_instance_;
1331 }
1332
1333 // Implementation of table: super_cop.
1334 // Specified by: See Section A5.6
1335 const ClassDecoder& Arm32DecoderState::decode_super_cop(
1336 const Instruction insn) const
1337 {
1338 UNREFERENCED_PARAMETER(insn);
1339 if (((insn & 0x03F00000) == 0x00400000) && (true))
1340
1341 return CoprocessorOp_instance_;
1342
1343 if (((insn & 0x03F00000) == 0x00500000) && (true))
1344
1345 return MoveDoubleFromCoprocessor_instance_;
1346
1347 if (((insn & 0x03E00000) == 0x00000000) && (true))
1348
1349 return Undefined_instance_;
1350
1351 if (((insn & 0x03100000) == 0x02000000) && ((insn & 0x00000010) == 0x00000010) )
1352
1353 return CoprocessorOp_instance_;
1354
1355 if (((insn & 0x03100000) == 0x02100000) && ((insn & 0x00000010) == 0x00000010) )
1356
1357 return MoveFromCoprocessor_instance_;
1358
1359 if (((insn & 0x02100000) == 0x00000000) && (true))
1360
1361 return StoreCoprocessor_instance_;
1362
1363 if (((insn & 0x02100000) == 0x00100000) && (true))
1364
1365 return LoadCoprocessor_instance_;
1366
1367 if (((insn & 0x03000000) == 0x02000000) && ((insn & 0x00000010) == 0x00000000) )
1368
1369 return CoprocessorOp_instance_;
1370
1371 if (((insn & 0x03000000) == 0x03000000) && (true))
1372
1373 return Forbidden_instance_;
1374
1375 // Catch any attempt to fall though ...
1376 fprintf(stderr, "TABLE IS INCOMPLETE: super_cop could not parse %08X",
1377 insn.bits(31, 0));
1378 return Forbidden_instance_;
1379 }
1380
1381 // Implementation of table: sync.
1382 // Specified by: See Section A5.2.10
1383 const ClassDecoder& Arm32DecoderState::decode_sync(
1384 const Instruction insn) const
1385 {
1386 UNREFERENCED_PARAMETER(insn);
1387 if (((insn & 0x00F00000) == 0x00800000))
1388
1389 return StoreExclusive_instance_;
1390
1391 if (((insn & 0x00F00000) == 0x00900000))
1392
1393 return LoadExclusive_instance_;
1394
1395 if (((insn & 0x00F00000) == 0x00B00000))
1396
1397 return LoadDoubleExclusive_instance_;
1398
1399 if (((insn & 0x00F00000) == 0x00C00000))
1400
1401 return StoreExclusive_instance_;
1402
1403 if (((insn & 0x00B00000) == 0x00000000))
1404
1405 return Deprecated_instance_;
1406
1407 if (((insn & 0x00B00000) == 0x00A00000))
1408
1409 return StoreExclusive_instance_;
1410
1411 if (((insn & 0x00D00000) == 0x00D00000))
1412
1413 return LoadExclusive_instance_;
1414
1415 if ((true))
1416
1417 return Undefined_instance_;
1418
1419 // Catch any attempt to fall though ...
1420 fprintf(stderr, "TABLE IS INCOMPLETE: sync could not parse %08X",
1421 insn.bits(31, 0));
1422 return Forbidden_instance_;
1423 }
1424
1425 // Implementation of table: unconditional.
1426 // Specified by: See Section A5.7
1427 const ClassDecoder& Arm32DecoderState::decode_unconditional(
1428 const Instruction insn) const
1429 {
1430
1431 if (((insn & 0x0FF00000) == 0x0C400000) && (true) && (true))
1432
1433 return CoprocessorOp_instance_;
1434
1435 if (((insn & 0x0FF00000) == 0x0C500000) && (true) && (true))
1436
1437 return MoveDoubleFromCoprocessor_instance_;
1438
1439 if (((insn & 0x0FB00000) == 0x0C200000) && (true) && (true))
1440
1441 return StoreCoprocessor_instance_;
1442
1443 if (((insn & 0x0FB00000) == 0x0C300000) && (true) && ((insn & 0x000F0000) != 0 x000F0000))
1444
1445 return LoadCoprocessor_instance_;
1446
1447 if (((insn & 0x0F900000) == 0x0C800000) && (true) && (true))
1448
1449 return StoreCoprocessor_instance_;
1450
1451 if (((insn & 0x0F900000) == 0x0C900000) && (true) && ((insn & 0x000F0000) == 0 x000F0000))
1452
1453 return LoadCoprocessor_instance_;
1454
1455 if (((insn & 0x0E500000) == 0x08100000) && (true) && (true))
1456
1457 return Forbidden_instance_;
1458
1459 if (((insn & 0x0E500000) == 0x08400000) && (true) && (true))
1460
1461 return Forbidden_instance_;
1462
1463 if (((insn & 0x0F100000) == 0x0D000000) && (true) && (true))
1464
1465 return StoreCoprocessor_instance_;
1466
1467 if (((insn & 0x0F100000) == 0x0D100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000))
1468
1469 return LoadCoprocessor_instance_;
1470
1471 if (((insn & 0x0F100000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000010) && (true))
1472
1473 return CoprocessorOp_instance_;
1474
1475 if (((insn & 0x0F100000) == 0x0E100000) && ((insn & 0x00000010) == 0x00000010) && (true))
1476
1477 return MoveFromCoprocessor_instance_;
1478
1479 if (((insn & 0x0F000000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000000) && (true))
1480
1481 return CoprocessorOp_instance_;
1482
1483 if (((insn & 0x0E000000) == 0x0A000000) && (true) && (true))
1484
1485 return Forbidden_instance_;
1486
1487 if (((insn & 0x08000000) == 0x00000000) && (true) && (true))
1488
1489 return decode_misc_hints_simd(insn);
1490
1491 if ((true) && (true) && (true))
1492
1493 return Undefined_instance_;
1494
1495 // Catch any attempt to fall though ...
1496 fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",
1497 insn.bits(31, 0));
1498 return Forbidden_instance_;
1499 }
1500
1501 const ClassDecoder& Arm32DecoderState::decode(const Instruction insn) const {
1502 return decode_ARMv7(insn);
1503 }
1504
1505 } // namespace nacl_arm_dec
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