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Side by Side Diff: src/trusted/validator_arm/gen/arm32_decode_named.cc

Issue 9960043: Finish separation of testing from sel_ldr validation. Also, automate (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 8 months ago
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1 /* 3 /*
2 * Copyright 2012 The Native Client Authors. All rights reserved. 4 * Copyright 2012 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can 5 * Use of this source code is governed by a BSD-style license that can
4 * be found in the LICENSE file. 6 * be found in the LICENSE file.
5 */ 7 */
6 8
7 /* 9 // DO NOT EDIT: GENERATED CODE
8 * DO NOT EDIT: GENERATED CODE 10
9 */ 11
10 12 #ifndef NACL_TRUSTED_BUT_NOT_TCB
11 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_named.h" 13 #error This file is not meant for use in the TCB
14 #endif
15
16
17 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_named_decoder .h"
12 18
13 #include <stdio.h> 19 #include <stdio.h>
14 20
15 namespace nacl_arm_dec { 21 using nacl_arm_dec::ClassDecoder;
16 22 using nacl_arm_dec::Instruction;
17 const char* NamedCoprocessorOp::name() const { 23
18 return "CoprocessorOp"; 24 namespace nacl_arm_test {
19 } 25
20 26 NamedArm32DecoderState::NamedArm32DecoderState()
21 const char* NamedImmediateBic::name() const { 27 : nacl_arm_dec::DecoderState()
22 return "ImmediateBic"; 28
23 } 29 , Binary3RegisterShiftedTest_instance_()
24 30
25 const char* NamedLoadMultiple::name() const { 31 , Binary4RegisterShiftedOp_instance_()
26 return "LoadMultiple"; 32
27 } 33 , Branch_instance_()
28 34
29 const char* NamedLoadCoprocessor::name() const { 35 , Breakpoint_instance_()
30 return "LoadCoprocessor"; 36
31 } 37 , BxBlx_instance_()
32 38
33 const char* NamedLoadDoubleExclusive::name() const { 39 , CoprocessorOp_instance_()
34 return "LoadDoubleExclusive"; 40
35 } 41 , DataProc_instance_()
36 42
37 const char* NamedBranch::name() const { 43 , Deprecated_instance_()
38 return "Branch"; 44
39 } 45 , EffectiveNoOp_instance_()
40 46
41 const char* NamedTest::name() const { 47 , Forbidden_instance_()
42 return "Test"; 48
43 } 49 , ImmediateBic_instance_()
44 50
45 const char* NamedStoreRegister::name() const { 51 , LoadCoprocessor_instance_()
46 return "StoreRegister"; 52
47 } 53 , LoadDoubleExclusive_instance_()
48 54
49 const char* NamedMoveDoubleFromCoprocessor::name() const { 55 , LoadDoubleI_instance_()
50 return "MoveDoubleFromCoprocessor"; 56
51 } 57 , LoadDoubleR_instance_()
52 58
53 const char* NamedTestImmediate::name() const { 59 , LoadExclusive_instance_()
54 return "TestImmediate"; 60
55 } 61 , LoadImmediate_instance_()
56 62
57 const char* NamedBxBlx::name() const { 63 , LoadMultiple_instance_()
58 return "BxBlx"; 64
59 } 65 , LoadRegister_instance_()
60 66
61 const char* NamedEffectiveNoOp::name() const { 67 , LongMultiply_instance_()
62 return "EffectiveNoOp"; 68
63 } 69 , MoveDoubleFromCoprocessor_instance_()
64 70
65 const char* NamedLongMultiply::name() const { 71 , MoveFromCoprocessor_instance_()
66 return "LongMultiply"; 72
67 } 73 , MoveToStatusRegister_instance_()
68 74
69 const char* NamedBinary4RegisterShiftedOp::name() const { 75 , Multiply_instance_()
70 return "Binary4RegisterShiftedOp"; 76
71 } 77 , PackSatRev_instance_()
72 78
73 const char* NamedBreakpoint::name() const { 79 , Roadblock_instance_()
74 return "Breakpoint"; 80
75 } 81 , SatAddSub_instance_()
76 82
77 const char* NamedMultiply::name() const { 83 , StoreCoprocessor_instance_()
78 return "Multiply"; 84
79 } 85 , StoreExclusive_instance_()
80 86
81 const char* NamedPackSatRev::name() const { 87 , StoreImmediate_instance_()
82 return "PackSatRev"; 88
83 } 89 , StoreRegister_instance_()
84 90
85 const char* NamedLoadExclusive::name() const { 91 , Test_instance_()
86 return "LoadExclusive"; 92
87 } 93 , TestImmediate_instance_()
88 94
89 const char* NamedVectorStore::name() const { 95 , Unary3RegisterShiftedOp_instance_()
90 return "VectorStore"; 96
91 } 97 , Undefined_instance_()
92 98
93 const char* NamedUnary3RegisterShiftedOp::name() const { 99 , Unpredictable_instance_()
94 return "Unary3RegisterShiftedOp"; 100
95 } 101 , VectorLoad_instance_()
96 102
97 const char* NamedUndefined::name() const { 103 , VectorStore_instance_()
98 return "Undefined"; 104
99 } 105 , Add_Rule_7_A1_P26Binary4RegisterShiftedOp_instance_()
100 106
101 const char* NamedDataProc::name() const { 107 {}
102 return "DataProc"; 108
103 } 109 NamedArm32DecoderState::~NamedArm32DecoderState() {}
104
105 const char* NamedDeprecated::name() const {
106 return "Deprecated";
107 }
108
109 const char* NamedLoadImmediate::name() const {
110 return "LoadImmediate";
111 }
112
113 const char* NamedStoreCoprocessor::name() const {
114 return "StoreCoprocessor";
115 }
116
117 const char* NamedRoadblock::name() const {
118 return "Roadblock";
119 }
120
121 const char* NamedLoadDoubleR::name() const {
122 return "LoadDoubleR";
123 }
124
125 const char* NamedStoreExclusive::name() const {
126 return "StoreExclusive";
127 }
128
129 const char* NamedStoreImmediate::name() const {
130 return "StoreImmediate";
131 }
132
133 const char* NamedMoveFromCoprocessor::name() const {
134 return "MoveFromCoprocessor";
135 }
136
137 const char* NamedLoadRegister::name() const {
138 return "LoadRegister";
139 }
140
141 const char* NamedLoadDoubleI::name() const {
142 return "LoadDoubleI";
143 }
144
145 const char* NamedBinary3RegisterShiftedTest::name() const {
146 return "Binary3RegisterShiftedTest";
147 }
148
149 const char* NamedUnpredictable::name() const {
150 return "Unpredictable";
151 }
152
153 const char* NamedForbidden::name() const {
154 return "Forbidden";
155 }
156
157 const char* NamedVectorLoad::name() const {
158 return "VectorLoad";
159 }
160
161 const char* NamedMoveToStatusRegister::name() const {
162 return "MoveToStatusRegister";
163 }
164
165 const char* NamedSatAddSub::name() const {
166 return "SatAddSub";
167 }
168
169 /*
170 * Prototypes for static table-matching functions.
171 */
172 static inline const ClassDecoder &decode_ARMv7(
173 const Instruction insn, const NamedArm32DecoderState *state);
174
175 static inline const ClassDecoder &decode_dp_misc(
176 const Instruction insn, const NamedArm32DecoderState *state);
177
178 static inline const ClassDecoder &decode_dp_reg(
179 const Instruction insn, const NamedArm32DecoderState *state);
180
181 static inline const ClassDecoder &decode_dp_reg_shifted(
182 const Instruction insn, const NamedArm32DecoderState *state);
183
184 static inline const ClassDecoder &decode_dp_immed(
185 const Instruction insn, const NamedArm32DecoderState *state);
186
187 static inline const ClassDecoder &decode_mult(
188 const Instruction insn, const NamedArm32DecoderState *state);
189
190 static inline const ClassDecoder &decode_sat_add_sub(
191 const Instruction insn, const NamedArm32DecoderState *state);
192
193 static inline const ClassDecoder &decode_half_mult(
194 const Instruction insn, const NamedArm32DecoderState *state);
195
196 static inline const ClassDecoder &decode_extra_load_store(
197 const Instruction insn, const NamedArm32DecoderState *state);
198
199 static inline const ClassDecoder &decode_sync(
200 const Instruction insn, const NamedArm32DecoderState *state);
201
202 static inline const ClassDecoder &decode_msr_and_hints(
203 const Instruction insn, const NamedArm32DecoderState *state);
204
205 static inline const ClassDecoder &decode_misc(
206 const Instruction insn, const NamedArm32DecoderState *state);
207
208 static inline const ClassDecoder &decode_load_store_word_byte(
209 const Instruction insn, const NamedArm32DecoderState *state);
210
211 static inline const ClassDecoder &decode_media(
212 const Instruction insn, const NamedArm32DecoderState *state);
213
214 static inline const ClassDecoder &decode_parallel_add_sub(
215 const Instruction insn, const NamedArm32DecoderState *state);
216
217 static inline const ClassDecoder &decode_pack_sat_rev(
218 const Instruction insn, const NamedArm32DecoderState *state);
219
220 static inline const ClassDecoder &decode_signed_mult(
221 const Instruction insn, const NamedArm32DecoderState *state);
222
223 static inline const ClassDecoder &decode_branch_block_xfer(
224 const Instruction insn, const NamedArm32DecoderState *state);
225
226 static inline const ClassDecoder &decode_super_cop(
227 const Instruction insn, const NamedArm32DecoderState *state);
228
229 static inline const ClassDecoder &decode_unconditional(
230 const Instruction insn, const NamedArm32DecoderState *state);
231
232 static inline const ClassDecoder &decode_misc_hints_simd(
233 const Instruction insn, const NamedArm32DecoderState *state);
234
235 static inline const ClassDecoder &decode_simd_dp(
236 const Instruction insn, const NamedArm32DecoderState *state);
237
238 static inline const ClassDecoder &decode_simd_dp_3same(
239 const Instruction insn, const NamedArm32DecoderState *state);
240
241 static inline const ClassDecoder &decode_simd_dp_3diff(
242 const Instruction insn, const NamedArm32DecoderState *state);
243
244 static inline const ClassDecoder &decode_simd_dp_2scalar(
245 const Instruction insn, const NamedArm32DecoderState *state);
246
247 static inline const ClassDecoder &decode_simd_dp_2shift(
248 const Instruction insn, const NamedArm32DecoderState *state);
249
250 static inline const ClassDecoder &decode_simd_dp_2misc(
251 const Instruction insn, const NamedArm32DecoderState *state);
252
253 static inline const ClassDecoder &decode_simd_dp_1imm(
254 const Instruction insn, const NamedArm32DecoderState *state);
255
256 static inline const ClassDecoder &decode_simd_load_store(
257 const Instruction insn, const NamedArm32DecoderState *state);
258
259 static inline const ClassDecoder &decode_simd_load_store_l0(
260 const Instruction insn, const NamedArm32DecoderState *state);
261
262 static inline const ClassDecoder &decode_simd_load_store_l1(
263 const Instruction insn, const NamedArm32DecoderState *state);
264
265 /*
266 * Table-matching function implementations.
267 */
268 110
269 /* 111 /*
270 * Implementation of table ARMv7. 112 * Implementation of table ARMv7.
271 * Specified by: See Section A5.1. 113 * Specified by: ('See Section A5.1',)
272 */ 114 */
273 static inline const ClassDecoder &decode_ARMv7( 115 const NamedClassDecoder& NamedArm32DecoderState::decode_ARMv7(
274 const Instruction insn, const NamedArm32DecoderState *state) { 116 const nacl_arm_dec::Instruction insn) const {
117
118 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x00000000) && (true)) {
119 return decode_dp_misc(insn);
120 }
121
122 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x0C000000) && (true)) {
123 return decode_super_cop(insn);
124 }
125
126 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000010)) {
127 return decode_media(insn);
128 }
129
275 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x04000000) && (true)) { 130 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x04000000) && (true)) {
276 return decode_load_store_word_byte(insn, state); 131 return decode_load_store_word_byte(insn);
277 } 132 }
278 133
279 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000000)) { 134 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000000)) {
280 return decode_load_store_word_byte(insn, state); 135 return decode_load_store_word_byte(insn);
281 } 136 }
282 137
283 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0E000000) == 0x06000000) && ((insn & 0x00000010) == 0x00000010)) {
284 return decode_media(insn, state);
285 }
286
287 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x00000000) && (true)) {
288 return decode_dp_misc(insn, state);
289 }
290
291 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x08000000) && (true)) { 138 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x08000000) && (true)) {
292 return decode_branch_block_xfer(insn, state); 139 return decode_branch_block_xfer(insn);
293 } 140 }
294 141
295 if (((insn & 0xF0000000) != 0xF0000000) && ((insn & 0x0C000000) == 0x0C000000) && (true)) {
296 return decode_super_cop(insn, state);
297 }
298
299 if (((insn & 0xF0000000) == 0xF0000000) && (true) && (true)) { 142 if (((insn & 0xF0000000) == 0xF0000000) && (true) && (true)) {
300 return decode_unconditional(insn, state); 143 return decode_unconditional(insn);
301 } 144 }
302 145
303 // Catch any attempt to fall through... 146 // Catch any attempt to fall through...
304 fprintf(stderr, "TABLE IS INCOMPLETE: ARMv7 could not parse %08X",insn.bits(31 ,0)); 147 fprintf(stderr, "TABLE IS INCOMPLETE: ARMv7 could not parse %08X",
305 return state->Forbidden_instance_; 148 insn.bits(31,0));
306 } 149 return Forbidden_instance_;
150 }
151
152
153 /*
154 * Implementation of table branch_block_xfer.
155 * Specified by: ('See Section A5.5',)
156 */
157 const NamedClassDecoder& NamedArm32DecoderState::decode_branch_block_xfer(
158 const nacl_arm_dec::Instruction insn) const {
159 UNREFERENCED_PARAMETER(insn);
160 if (((insn & 0x02500000) == 0x00100000)) {
161 return LoadMultiple_instance_;
162 }
163
164 if (((insn & 0x02000000) == 0x02000000)) {
165 return Branch_instance_;
166 }
167
168 if (((insn & 0x02500000) == 0x00000000)) {
169 return StoreImmediate_instance_;
170 }
171
172 if (((insn & 0x02400000) == 0x00400000)) {
173 return Forbidden_instance_;
174 }
175
176 // Catch any attempt to fall through...
177 fprintf(stderr, "TABLE IS INCOMPLETE: branch_block_xfer could not parse %08X",
178 insn.bits(31,0));
179 return Forbidden_instance_;
180 }
181
182
183 /*
184 * Implementation of table dp_immed.
185 * Specified by: ('See Section A5.2.3',)
186 */
187 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_immed(
188 const nacl_arm_dec::Instruction insn) const {
189 UNREFERENCED_PARAMETER(insn);
190 if (((insn & 0x01E00000) == 0x01E00000)) {
191 return DataProc_instance_;
192 }
193
194 if (((insn & 0x01C00000) == 0x00000000)) {
195 return DataProc_instance_;
196 }
197
198 if (((insn & 0x01400000) == 0x00400000)) {
199 return DataProc_instance_;
200 }
201
202 if (((insn & 0x00C00000) == 0x00800000)) {
203 return DataProc_instance_;
204 }
205
206 if (((insn & 0x01F00000) == 0x01500000)) {
207 return Test_instance_;
208 }
209
210 if (((insn & 0x01B00000) == 0x01300000)) {
211 return Test_instance_;
212 }
213
214 if (((insn & 0x01F00000) == 0x01100000)) {
215 return TestImmediate_instance_;
216 }
217
218 if (((insn & 0x01E00000) == 0x01C00000)) {
219 return ImmediateBic_instance_;
220 }
221
222 // Catch any attempt to fall through...
223 fprintf(stderr, "TABLE IS INCOMPLETE: dp_immed could not parse %08X",
224 insn.bits(31,0));
225 return Forbidden_instance_;
226 }
227
307 228
308 /* 229 /*
309 * Implementation of table dp_misc. 230 * Implementation of table dp_misc.
310 * Specified by: See Section A5.2. 231 * Specified by: ('See Section A5.2',)
311 */ 232 */
312 static inline const ClassDecoder &decode_dp_misc( 233 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_misc(
313 const Instruction insn, const NamedArm32DecoderState *state) { 234 const nacl_arm_dec::Instruction insn) const {
235
236 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000010) == 0x00000000)) {
237 return decode_dp_reg(insn);
238 }
239
240 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000080) == 0x00000000)) {
241 return decode_misc(insn);
242 }
243
244 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01900000) != 0x01000000) && (true)) {
245 return decode_dp_immed(insn);
246 }
247
248 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000090) == 0x00000080)) {
249 return decode_half_mult(insn);
250 }
251
252 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01000000) && (true)) {
253 return DataProc_instance_;
254 }
255
256 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
257 return Forbidden_instance_;
258 }
259
260 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
261 return Forbidden_instance_;
262 }
263
264 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
265 return decode_extra_load_store(insn);
266 }
267
268 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
269 return decode_extra_load_store(insn);
270 }
271
272 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01200000) && (true)) {
273 return decode_msr_and_hints(insn);
274 }
275
276 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000090)) {
277 return decode_sync(insn);
278 }
279
314 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000090) == 0x00000010)) { 280 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000090) == 0x00000010)) {
315 return decode_dp_reg_shifted(insn, state); 281 return decode_dp_reg_shifted(insn);
316 } 282 }
317 283
318 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) != 0x01000000) && ((insn & 0x00000010) == 0x00000000)) {
319 return decode_dp_reg(insn, state);
320 }
321
322 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000090) == 0x00000080)) {
323 return decode_half_mult(insn, state);
324 }
325
326 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01900000) == 0x01000000) && ((insn & 0x00000080) == 0x00000000)) {
327 return decode_misc(insn, state);
328 }
329
330 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
331 return decode_extra_load_store(insn, state);
332 }
333
334 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) != 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
335 return decode_extra_load_store(insn, state);
336 }
337
338 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000F0) == 0x000000B0)) {
339 return state->Forbidden_instance_;
340 }
341
342 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x000000D0) == 0x000000D0)) {
343 return state->Forbidden_instance_;
344 }
345
346 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x000000F0) == 0x00000090)) { 284 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x000000F0) == 0x00000090)) {
347 return decode_mult(insn, state); 285 return decode_mult(insn);
348 } 286 }
349 287
350 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000090)) { 288 // Catch any attempt to fall through...
351 return decode_sync(insn, state); 289 fprintf(stderr, "TABLE IS INCOMPLETE: dp_misc could not parse %08X",
352 } 290 insn.bits(31,0));
353 291 return Forbidden_instance_;
354 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01000000) && (true)) { 292 }
355 return state->DataProc_instance_; 293
356 }
357
358 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01B00000) == 0x01200000) && (true)) {
359 return decode_msr_and_hints(insn, state);
360 }
361
362 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01900000) != 0x01000000) && (true)) {
363 return decode_dp_immed(insn, state);
364 }
365
366 // Catch any attempt to fall through...
367 fprintf(stderr, "TABLE IS INCOMPLETE: dp_misc could not parse %08X",insn.bits( 31,0));
368 return state->Forbidden_instance_;
369 }
370 294
371 /* 295 /*
372 * Implementation of table dp_reg. 296 * Implementation of table dp_reg.
373 * Specified by: See Section A5.2.1. 297 * Specified by: ('See Section A5.2.1',)
374 */ 298 */
375 static inline const ClassDecoder &decode_dp_reg( 299 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_reg(
376 const Instruction insn, const NamedArm32DecoderState *state) { 300 const nacl_arm_dec::Instruction insn) const {
301 UNREFERENCED_PARAMETER(insn);
302 if (((insn & 0x01800000) == 0x01800000)) {
303 return DataProc_instance_;
304 }
305
306 if (((insn & 0x01000000) == 0x00000000)) {
307 return DataProc_instance_;
308 }
309
377 if (((insn & 0x01900000) == 0x01100000)) { 310 if (((insn & 0x01900000) == 0x01100000)) {
378 return state->Test_instance_; 311 return Test_instance_;
379 } 312 }
380 313
381 if (((insn & 0x01800000) == 0x01800000)) { 314 // Catch any attempt to fall through...
382 return state->DataProc_instance_; 315 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",
383 } 316 insn.bits(31,0));
384 317 return Forbidden_instance_;
385 if (((insn & 0x01000000) == 0x00000000)) { 318 }
386 return state->DataProc_instance_; 319
387 }
388
389 // Catch any attempt to fall through...
390 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",insn.bits(3 1,0));
391 return state->Forbidden_instance_;
392 }
393 320
394 /* 321 /*
395 * Implementation of table dp_reg_shifted. 322 * Implementation of table dp_reg_shifted.
396 * Specified by: See Section A5.2.2. 323 * Specified by: ('See Section A5.2.2',)
397 */ 324 */
398 static inline const ClassDecoder &decode_dp_reg_shifted( 325 const NamedClassDecoder& NamedArm32DecoderState::decode_dp_reg_shifted(
399 const Instruction insn, const NamedArm32DecoderState *state) { 326 const nacl_arm_dec::Instruction insn) const {
327 UNREFERENCED_PARAMETER(insn);
328 if (((insn & 0x01E00000) == 0x01800000)) {
329 return Binary4RegisterShiftedOp_instance_;
330 }
331
332 if (((insn & 0x01A00000) == 0x00A00000)) {
333 return Binary4RegisterShiftedOp_instance_;
334 }
335
336 if (((insn & 0x00E00000) == 0x00C00000)) {
337 return Binary4RegisterShiftedOp_instance_;
338 }
339
340 if (((insn & 0x01800000) == 0x00000000)) {
341 return Binary4RegisterShiftedOp_instance_;
342 }
343
400 if (((insn & 0x01E00000) == 0x01A00000)) { 344 if (((insn & 0x01E00000) == 0x01A00000)) {
401 return state->DataProc_instance_; 345 return DataProc_instance_;
402 } 346 }
403 347
348 if (((insn & 0x01900000) == 0x01100000)) {
349 return Binary3RegisterShiftedTest_instance_;
350 }
351
404 if (((insn & 0x01E00000) == 0x01E00000)) { 352 if (((insn & 0x01E00000) == 0x01E00000)) {
405 return state->Unary3RegisterShiftedOp_instance_; 353 return Unary3RegisterShiftedOp_instance_;
406 } 354 }
407 355
408 if (((insn & 0x01900000) == 0x01100000)) { 356 if (((insn & 0x01E00000) == 0x00800000)) {
409 return state->Binary3RegisterShiftedTest_instance_; 357 return Add_Rule_7_A1_P26Binary4RegisterShiftedOp_instance_;
410 } 358 }
411 359
412 if (((insn & 0x01A00000) == 0x01800000)) { 360 // Catch any attempt to fall through...
413 return state->Binary4RegisterShiftedOp_instance_; 361 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg_shifted could not parse %08X",
414 } 362 insn.bits(31,0));
415 363 return Forbidden_instance_;
416 if (((insn & 0x01000000) == 0x00000000)) { 364 }
417 return state->Binary4RegisterShiftedOp_instance_; 365
418 } 366
419 367 /*
420 // Catch any attempt to fall through... 368 * Implementation of table extra_load_store.
421 fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg_shifted could not parse %08X",ins n.bits(31,0)); 369 * Specified by: ('See Section A5.2.8',)
422 return state->Forbidden_instance_; 370 */
423 } 371 const NamedClassDecoder& NamedArm32DecoderState::decode_extra_load_store(
424 372 const nacl_arm_dec::Instruction insn) const {
425 /* 373 UNREFERENCED_PARAMETER(insn);
426 * Implementation of table dp_immed. 374 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00400000) ) {
427 * Specified by: See Section A5.2.3. 375 return LoadDoubleI_instance_;
428 */ 376 }
429 static inline const ClassDecoder &decode_dp_immed( 377
430 const Instruction insn, const NamedArm32DecoderState *state) { 378 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00100000) ) {
431 if (((insn & 0x01F00000) == 0x01100000)) { 379 return LoadRegister_instance_;
432 return state->TestImmediate_instance_; 380 }
433 } 381
434 382 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00100000) ) {
435 if (((insn & 0x01F00000) == 0x01500000)) { 383 return LoadRegister_instance_;
436 return state->Test_instance_; 384 }
437 } 385
438 386 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00000000) ) {
439 if (((insn & 0x01B00000) == 0x01300000)) { 387 return LoadDoubleR_instance_;
440 return state->Test_instance_; 388 }
441 } 389
442 390 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00400000) ) {
443 if (((insn & 0x01E00000) == 0x01C00000)) { 391 return StoreImmediate_instance_;
444 return state->ImmediateBic_instance_; 392 }
445 } 393
446 394 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00000000) ) {
447 if (((insn & 0x01E00000) == 0x01E00000)) { 395 return StoreRegister_instance_;
448 return state->DataProc_instance_; 396 }
449 } 397
450 398 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00500000) ) {
451 if (((insn & 0x01C00000) == 0x00000000)) { 399 return LoadImmediate_instance_;
452 return state->DataProc_instance_; 400 }
453 } 401
454 402 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00500000) ) {
455 if (((insn & 0x00C00000) == 0x00800000)) { 403 return LoadImmediate_instance_;
456 return state->DataProc_instance_; 404 }
457 } 405
458 406 // Catch any attempt to fall through...
459 if (((insn & 0x01400000) == 0x00400000)) { 407 fprintf(stderr, "TABLE IS INCOMPLETE: extra_load_store could not parse %08X",
460 return state->DataProc_instance_; 408 insn.bits(31,0));
461 } 409 return Forbidden_instance_;
462 410 }
463 // Catch any attempt to fall through... 411
464 fprintf(stderr, "TABLE IS INCOMPLETE: dp_immed could not parse %08X",insn.bits (31,0)); 412
465 return state->Forbidden_instance_; 413 /*
466 } 414 * Implementation of table half_mult.
415 * Specified by: ('See Section A5.2.7',)
416 */
417 const NamedClassDecoder& NamedArm32DecoderState::decode_half_mult(
418 const nacl_arm_dec::Instruction insn) const {
419 UNREFERENCED_PARAMETER(insn);
420 if (((insn & 0x00600000) == 0x00400000)) {
421 return LongMultiply_instance_;
422 }
423
424 if (((insn & 0x00600000) == 0x00600000)) {
425 return Multiply_instance_;
426 }
427
428 if (((insn & 0x00400000) == 0x00000000)) {
429 return Multiply_instance_;
430 }
431
432 // Catch any attempt to fall through...
433 fprintf(stderr, "TABLE IS INCOMPLETE: half_mult could not parse %08X",
434 insn.bits(31,0));
435 return Forbidden_instance_;
436 }
437
438
439 /*
440 * Implementation of table load_store_word_byte.
441 * Specified by: ('See Section A5.3',)
442 */
443 const NamedClassDecoder& NamedArm32DecoderState::decode_load_store_word_byte(
444 const nacl_arm_dec::Instruction insn) const {
445 UNREFERENCED_PARAMETER(insn);
446 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00100000) && (true)) {
447 return LoadImmediate_instance_;
448 }
449
450 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00000000) && (true)) {
451 return StoreImmediate_instance_;
452 }
453
454 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000010) == 0x00000000)) {
455 return LoadRegister_instance_;
456 }
457
458 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && (true)) {
459 return Forbidden_instance_;
460 }
461
462 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x00000010) == 0x00000000)) {
463 return Forbidden_instance_;
464 }
465
466 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
467 return StoreRegister_instance_;
468 }
469
470 // Catch any attempt to fall through...
471 fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08 X",
472 insn.bits(31,0));
473 return Forbidden_instance_;
474 }
475
476
477 /*
478 * Implementation of table media.
479 * Specified by: ('See Section A5.4',)
480 */
481 const NamedClassDecoder& NamedArm32DecoderState::decode_media(
482 const nacl_arm_dec::Instruction insn) const {
483
484 if ((true) && (true)) {
485 return Undefined_instance_;
486 }
487
488 if (((insn & 0x01800000) == 0x00800000) && (true)) {
489 return decode_pack_sat_rev(insn);
490 }
491
492 if (((insn & 0x01800000) == 0x00000000) && (true)) {
493 return decode_parallel_add_sub(insn);
494 }
495
496 if (((insn & 0x01800000) == 0x01000000) && (true)) {
497 return decode_signed_mult(insn);
498 }
499
500 if (((insn & 0x01A00000) == 0x01A00000) && ((insn & 0x00000060) == 0x00000040) ) {
501 return DataProc_instance_;
502 }
503
504 if (((insn & 0x01E00000) == 0x01C00000) && ((insn & 0x00000060) == 0x00000000) ) {
505 return DataProc_instance_;
506 }
507
508 if (((insn & 0x01F00000) == 0x01F00000) && ((insn & 0x000000E0) == 0x000000E0) ) {
509 return Roadblock_instance_;
510 }
511
512 if (((insn & 0x01F00000) == 0x01800000) && ((insn & 0x000000E0) == 0x00000000) ) {
513 return Multiply_instance_;
514 }
515
516 // Catch any attempt to fall through...
517 fprintf(stderr, "TABLE IS INCOMPLETE: media could not parse %08X",
518 insn.bits(31,0));
519 return Forbidden_instance_;
520 }
521
522
523 /*
524 * Implementation of table misc.
525 * Specified by: ('See Section A5.2.12',)
526 */
527 const NamedClassDecoder& NamedArm32DecoderState::decode_misc(
528 const nacl_arm_dec::Instruction insn) const {
529
530 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00200000) && (true)) {
531 return BxBlx_instance_;
532 }
533
534 if ((true) && (true) && (true)) {
535 return Undefined_instance_;
536 }
537
538 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00600000) && (true)) {
539 return DataProc_instance_;
540 }
541
542 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00000000)) {
543 return MoveToStatusRegister_instance_;
544 }
545
546 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00200000) == 0x00000000) && (true)) {
547 return DataProc_instance_;
548 }
549
550 if (((insn & 0x00000070) == 0x00000050) && (true) && (true)) {
551 return decode_sat_add_sub(insn);
552 }
553
554 if (((insn & 0x00000070) == 0x00000030) && ((insn & 0x00600000) == 0x00200000) && (true)) {
555 return BxBlx_instance_;
556 }
557
558 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00010000)) {
559 return Forbidden_instance_;
560 }
561
562 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00020000) == 0x00020000)) {
563 return Forbidden_instance_;
564 }
565
566 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00600000) && (true)) {
567 return Forbidden_instance_;
568 }
569
570 if (((insn & 0x00000070) == 0x00000020) && ((insn & 0x00600000) == 0x00200000) && (true)) {
571 return Forbidden_instance_;
572 }
573
574 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00600000) && (true)) {
575 return Forbidden_instance_;
576 }
577
578 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00200000) && (true)) {
579 return Breakpoint_instance_;
580 }
581
582 // Catch any attempt to fall through...
583 fprintf(stderr, "TABLE IS INCOMPLETE: misc could not parse %08X",
584 insn.bits(31,0));
585 return Forbidden_instance_;
586 }
587
588
589 /*
590 * Implementation of table misc_hints_simd.
591 * Specified by: ('See Section A5.7.1',)
592 */
593 const NamedClassDecoder& NamedArm32DecoderState::decode_misc_hints_simd(
594 const nacl_arm_dec::Instruction insn) const {
595
596 if (((insn & 0x06000000) == 0x02000000) && (true) && (true)) {
597 return decode_simd_dp(insn);
598 }
599
600 if (((insn & 0x07700000) == 0x04500000) && (true) && (true)) {
601 return EffectiveNoOp_instance_;
602 }
603
604 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000050) && (true)) {
605 return EffectiveNoOp_instance_;
606 }
607
608 if (((insn & 0x07700000) == 0x06500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
609 return EffectiveNoOp_instance_;
610 }
611
612 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000D0) == 0x00000040) && (true)) {
613 return EffectiveNoOp_instance_;
614 }
615
616 if ((true) && (true) && (true)) {
617 return Undefined_instance_;
618 }
619
620 if (((insn & 0x07100000) == 0x04000000) && (true) && (true)) {
621 return decode_simd_load_store(insn);
622 }
623
624 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
625 return Unpredictable_instance_;
626 }
627
628 if (((insn & 0x06300000) == 0x04300000) && (true) && (true)) {
629 return Unpredictable_instance_;
630 }
631
632 if (((insn & 0x06300000) == 0x06300000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
633 return Unpredictable_instance_;
634 }
635
636 if (((insn & 0x07700000) == 0x07500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
637 return EffectiveNoOp_instance_;
638 }
639
640 if (((insn & 0x07700000) == 0x05500000) && (true) && (true)) {
641 return EffectiveNoOp_instance_;
642 }
643
644 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000010) && (true)) {
645 return EffectiveNoOp_instance_;
646 }
647
648 if (((insn & 0x07700000) == 0x04100000) && (true) && (true)) {
649 return EffectiveNoOp_instance_;
650 }
651
652 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
653 return EffectiveNoOp_instance_;
654 }
655
656 if (((insn & 0x06700000) == 0x06100000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
657 return EffectiveNoOp_instance_;
658 }
659
660 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x00000020) == 0x00000000) && ((insn & 0x00010000) == 0x00000000)) {
661 return Forbidden_instance_;
662 }
663
664 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000000) && ((insn & 0x00010000) == 0x00010000)) {
665 return Forbidden_instance_;
666 }
667
668 // Catch any attempt to fall through...
669 fprintf(stderr, "TABLE IS INCOMPLETE: misc_hints_simd could not parse %08X",
670 insn.bits(31,0));
671 return Forbidden_instance_;
672 }
673
674
675 /*
676 * Implementation of table msr_and_hints.
677 * Specified by: ('See Section A5.2.11',)
678 */
679 const NamedClassDecoder& NamedArm32DecoderState::decode_msr_and_hints(
680 const nacl_arm_dec::Instruction insn) const {
681 UNREFERENCED_PARAMETER(insn);
682 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000002)) {
683 return EffectiveNoOp_instance_;
684 }
685
686 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000004)) {
687 return EffectiveNoOp_instance_;
688 }
689
690 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FD) == 0x00000001)) {
691 return EffectiveNoOp_instance_;
692 }
693
694 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000000)) {
695 return EffectiveNoOp_instance_;
696 }
697
698 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00030000) == 0x00010000) && (true)) {
699 return Forbidden_instance_;
700 }
701
702 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00020000) == 0x00020000) && (true)) {
703 return Forbidden_instance_;
704 }
705
706 if (((insn & 0x00400000) == 0x00400000) && (true) && (true)) {
707 return Forbidden_instance_;
708 }
709
710 if ((true) && (true) && (true)) {
711 return Forbidden_instance_;
712 }
713
714 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000F0) == 0x000000F0)) {
715 return EffectiveNoOp_instance_;
716 }
717
718 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00040000) && (true)) {
719 return MoveToStatusRegister_instance_;
720 }
721
722 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000B0000) == 0x00080000) && (true)) {
723 return MoveToStatusRegister_instance_;
724 }
725
726 // Catch any attempt to fall through...
727 fprintf(stderr, "TABLE IS INCOMPLETE: msr_and_hints could not parse %08X",
728 insn.bits(31,0));
729 return Forbidden_instance_;
730 }
731
467 732
468 /* 733 /*
469 * Implementation of table mult. 734 * Implementation of table mult.
470 * Specified by: See Section A5.2.5. 735 * Specified by: ('See Section A5.2.5',)
471 */ 736 */
472 static inline const ClassDecoder &decode_mult( 737 const NamedClassDecoder& NamedArm32DecoderState::decode_mult(
473 const Instruction insn, const NamedArm32DecoderState *state) { 738 const nacl_arm_dec::Instruction insn) const {
739 UNREFERENCED_PARAMETER(insn);
740 if (((insn & 0x00C00000) == 0x00000000)) {
741 return Multiply_instance_;
742 }
743
744 if (((insn & 0x00800000) == 0x00800000)) {
745 return LongMultiply_instance_;
746 }
747
748 if (((insn & 0x00D00000) == 0x00500000)) {
749 return Undefined_instance_;
750 }
751
474 if (((insn & 0x00F00000) == 0x00400000)) { 752 if (((insn & 0x00F00000) == 0x00400000)) {
475 return state->LongMultiply_instance_; 753 return LongMultiply_instance_;
476 } 754 }
477 755
478 if (((insn & 0x00F00000) == 0x00600000)) { 756 if (((insn & 0x00F00000) == 0x00600000)) {
479 return state->Multiply_instance_; 757 return Multiply_instance_;
480 } 758 }
481 759
482 if (((insn & 0x00D00000) == 0x00500000)) { 760 // Catch any attempt to fall through...
483 return state->Undefined_instance_; 761 fprintf(stderr, "TABLE IS INCOMPLETE: mult could not parse %08X",
484 } 762 insn.bits(31,0));
485 763 return Forbidden_instance_;
486 if (((insn & 0x00C00000) == 0x00000000)) { 764 }
487 return state->Multiply_instance_; 765
488 } 766
489 767 /*
490 if (((insn & 0x00800000) == 0x00800000)) { 768 * Implementation of table pack_sat_rev.
491 return state->LongMultiply_instance_; 769 * Specified by: ('See Section A5.4.3',)
492 } 770 */
493 771 const NamedClassDecoder& NamedArm32DecoderState::decode_pack_sat_rev(
494 // Catch any attempt to fall through... 772 const nacl_arm_dec::Instruction insn) const {
495 fprintf(stderr, "TABLE IS INCOMPLETE: mult could not parse %08X",insn.bits(31, 0)); 773 UNREFERENCED_PARAMETER(insn);
496 return state->Forbidden_instance_; 774 if (((insn & 0x00700000) == 0x00700000) && ((insn & 0x000000E0) == 0x00000020) ) {
497 } 775 return PackSatRev_instance_;
776 }
777
778 if ((true) && (true)) {
779 return Undefined_instance_;
780 }
781
782 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000020) == 0x00000000) ) {
783 return PackSatRev_instance_;
784 }
785
786 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000E0) == 0x000000A0) ) {
787 return PackSatRev_instance_;
788 }
789
790 if (((insn & 0x00200000) == 0x00200000) && ((insn & 0x00000020) == 0x00000000) ) {
791 return PackSatRev_instance_;
792 }
793
794 if (((insn & 0x00600000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000020) ) {
795 return PackSatRev_instance_;
796 }
797
798 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x000000A0) ) {
799 return PackSatRev_instance_;
800 }
801
802 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x000000E0) == 0x00000060) ) {
803 return PackSatRev_instance_;
804 }
805
806 if (((insn & 0x00700000) == 0x00600000) && ((insn & 0x000000A0) == 0x00000020) ) {
807 return PackSatRev_instance_;
808 }
809
810 if (((insn & 0x00500000) == 0x00000000) && ((insn & 0x000000E0) == 0x00000060) ) {
811 return PackSatRev_instance_;
812 }
813
814 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x00000060) ) {
815 return PackSatRev_instance_;
816 }
817
818 // Catch any attempt to fall through...
819 fprintf(stderr, "TABLE IS INCOMPLETE: pack_sat_rev could not parse %08X",
820 insn.bits(31,0));
821 return Forbidden_instance_;
822 }
823
824
825 /*
826 * Implementation of table parallel_add_sub.
827 * Specified by: ('See Sections A5.4.1, A5.4.2',)
828 */
829 const NamedClassDecoder& NamedArm32DecoderState::decode_parallel_add_sub(
830 const nacl_arm_dec::Instruction insn) const {
831 UNREFERENCED_PARAMETER(insn);
832 if ((true) && (true)) {
833 return Undefined_instance_;
834 }
835
836 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000080) ) {
837 return DataProc_instance_;
838 }
839
840 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x000000E0) ) {
841 return DataProc_instance_;
842 }
843
844 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x00000080) ) {
845 return DataProc_instance_;
846 }
847
848 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x000000E0) ) {
849 return DataProc_instance_;
850 }
851
852 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x00000080) == 0x00000000) ) {
853 return DataProc_instance_;
854 }
855
856 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000080) == 0x00000000) ) {
857 return DataProc_instance_;
858 }
859
860 // Catch any attempt to fall through...
861 fprintf(stderr, "TABLE IS INCOMPLETE: parallel_add_sub could not parse %08X",
862 insn.bits(31,0));
863 return Forbidden_instance_;
864 }
865
498 866
499 /* 867 /*
500 * Implementation of table sat_add_sub. 868 * Implementation of table sat_add_sub.
501 * Specified by: See Section A5.2.6. 869 * Specified by: ('See Section A5.2.6',)
502 */ 870 */
503 static inline const ClassDecoder &decode_sat_add_sub( 871 const NamedClassDecoder& NamedArm32DecoderState::decode_sat_add_sub(
504 const Instruction insn, const NamedArm32DecoderState *state) { 872 const nacl_arm_dec::Instruction insn) const {
873 UNREFERENCED_PARAMETER(insn);
505 if ((true)) { 874 if ((true)) {
506 return state->SatAddSub_instance_; 875 return SatAddSub_instance_;
507 } 876 }
508 877
509 // Catch any attempt to fall through... 878 // Catch any attempt to fall through...
510 fprintf(stderr, "TABLE IS INCOMPLETE: sat_add_sub could not parse %08X",insn.b its(31,0)); 879 fprintf(stderr, "TABLE IS INCOMPLETE: sat_add_sub could not parse %08X",
511 return state->Forbidden_instance_; 880 insn.bits(31,0));
512 } 881 return Forbidden_instance_;
513 882 }
514 /* 883
515 * Implementation of table half_mult. 884
516 * Specified by: See Section A5.2.7. 885 /*
517 */ 886 * Implementation of table signed_mult.
518 static inline const ClassDecoder &decode_half_mult( 887 * Specified by: ('See Section A5.4.4',)
519 const Instruction insn, const NamedArm32DecoderState *state) { 888 */
520 if (((insn & 0x00600000) == 0x00400000)) { 889 const NamedClassDecoder& NamedArm32DecoderState::decode_signed_mult(
521 return state->LongMultiply_instance_; 890 const nacl_arm_dec::Instruction insn) const {
522 } 891 UNREFERENCED_PARAMETER(insn);
523 892 if ((true) && (true) && (true)) {
524 if (((insn & 0x00600000) == 0x00600000)) { 893 return Undefined_instance_;
525 return state->Multiply_instance_; 894 }
526 } 895
527 896 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
528 if (((insn & 0x00400000) == 0x00000000)) { 897 return LongMultiply_instance_;
529 return state->Multiply_instance_; 898 }
530 } 899
531 900 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000C0) == 0x00000040) && ((insn & 0x0000F000) != 0x0000F000)) {
532 // Catch any attempt to fall through... 901 return Multiply_instance_;
533 fprintf(stderr, "TABLE IS INCOMPLETE: half_mult could not parse %08X",insn.bit s(31,0)); 902 }
534 return state->Forbidden_instance_; 903
535 } 904 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x000000C0) && (true)) {
536 905 return Multiply_instance_;
537 /* 906 }
538 * Implementation of table extra_load_store. 907
539 * Specified by: See Section A5.2.8. 908 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
540 */ 909 return Multiply_instance_;
541 static inline const ClassDecoder &decode_extra_load_store( 910 }
542 const Instruction insn, const NamedArm32DecoderState *state) { 911
543 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00000000) ) { 912 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x00000000) && (true)) {
544 return state->LoadDoubleR_instance_; 913 return Multiply_instance_;
545 } 914 }
546 915
547 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00100000) ) { 916 // Catch any attempt to fall through...
548 return state->LoadRegister_instance_; 917 fprintf(stderr, "TABLE IS INCOMPLETE: signed_mult could not parse %08X",
549 } 918 insn.bits(31,0));
550 919 return Forbidden_instance_;
551 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00400000) ) { 920 }
552 return state->LoadDoubleI_instance_; 921
553 } 922
554 923 /*
555 if (((insn & 0x00000060) == 0x00000040) && ((insn & 0x00500000) == 0x00500000) ) { 924 * Implementation of table simd_dp.
556 return state->LoadImmediate_instance_; 925 * Specified by: ('See Section A7.4',)
557 } 926 */
558 927 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp(
559 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00000000) ) { 928 const nacl_arm_dec::Instruction insn) const {
560 return state->StoreRegister_instance_; 929
561 } 930 if ((true) && (true) && (true) && (true)) {
562 931 return Undefined_instance_;
563 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00100000) ) { 932 }
564 return state->LoadRegister_instance_; 933
565 } 934 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
566 935 return decode_simd_dp_3diff(insn);
567 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00400000) ) { 936 }
568 return state->StoreImmediate_instance_; 937
569 } 938 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
570 939 return decode_simd_dp_3diff(insn);
571 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00500000) == 0x00500000) ) { 940 }
572 return state->LoadImmediate_instance_; 941
573 } 942 if ((true) && ((insn & 0x00800000) == 0x00000000) && (true) && (true)) {
574 943 return decode_simd_dp_3same(insn);
575 // Catch any attempt to fall through... 944 }
576 fprintf(stderr, "TABLE IS INCOMPLETE: extra_load_store could not parse %08X",i nsn.bits(31,0)); 945
577 return state->Forbidden_instance_; 946 if ((true) && ((insn & 0x00B80000) == 0x00880000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
578 } 947 return decode_simd_dp_2shift(insn);
948 }
949
950 if ((true) && ((insn & 0x00B00000) == 0x00900000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
951 return decode_simd_dp_2shift(insn);
952 }
953
954 if ((true) && ((insn & 0x00A00000) == 0x00A00000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
955 return decode_simd_dp_2shift(insn);
956 }
957
958 if ((true) && ((insn & 0x00800000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000090)) {
959 return decode_simd_dp_2shift(insn);
960 }
961
962 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
963 return decode_simd_dp_2scalar(insn);
964 }
965
966 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
967 return decode_simd_dp_2scalar(insn);
968 }
969
970 if ((true) && ((insn & 0x00B80000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
971 return decode_simd_dp_1imm(insn);
972 }
973
974 if (((insn & 0x01000000) == 0x00000000) && ((insn & 0x00B00000) == 0x00B00000) && (true) && ((insn & 0x00000010) == 0x00000000)) {
975 return EffectiveNoOp_instance_;
976 }
977
978 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000C00) == 0x00000800) && ((insn & 0x00000010) == 0x00000000)) {
979 return EffectiveNoOp_instance_;
980 }
981
982 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000F00) == 0x00000C00) && ((insn & 0x00000090) == 0x00000000)) {
983 return EffectiveNoOp_instance_;
984 }
985
986 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000800) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
987 return decode_simd_dp_2misc(insn);
988 }
989
990 // Catch any attempt to fall through...
991 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp could not parse %08X",
992 insn.bits(31,0));
993 return Forbidden_instance_;
994 }
995
996
997 /*
998 * Implementation of table simd_dp_1imm.
999 * Specified by: ('See Section A7.4.6',)
1000 */
1001 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_1imm(
1002 const nacl_arm_dec::Instruction insn) const {
1003 UNREFERENCED_PARAMETER(insn);
1004 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000F00) ) {
1005 return Undefined_instance_;
1006 }
1007
1008 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000E00) == 0x00000C00) ) {
1009 return EffectiveNoOp_instance_;
1010 }
1011
1012 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000E00) ) {
1013 return EffectiveNoOp_instance_;
1014 }
1015
1016 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000800) == 0x00000000) ) {
1017 return EffectiveNoOp_instance_;
1018 }
1019
1020 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000C00) == 0x00000800) ) {
1021 return EffectiveNoOp_instance_;
1022 }
1023
1024 if (((insn & 0x00000020) == 0x00000000) && (true)) {
1025 return EffectiveNoOp_instance_;
1026 }
1027
1028 // Catch any attempt to fall through...
1029 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_1imm could not parse %08X",
1030 insn.bits(31,0));
1031 return Forbidden_instance_;
1032 }
1033
1034
1035 /*
1036 * Implementation of table simd_dp_2misc.
1037 * Specified by: ('See Section A7.4.5',)
1038 */
1039 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_2misc(
1040 const nacl_arm_dec::Instruction insn) const {
1041 UNREFERENCED_PARAMETER(insn);
1042 if ((true) && (true)) {
1043 return Undefined_instance_;
1044 }
1045
1046 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000780) == 0x00000700) ) {
1047 return EffectiveNoOp_instance_;
1048 }
1049
1050 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000380) == 0x00000380) ) {
1051 return EffectiveNoOp_instance_;
1052 }
1053
1054 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000007C0) == 0x00000300) ) {
1055 return EffectiveNoOp_instance_;
1056 }
1057
1058 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000006C0) == 0x00000600) ) {
1059 return EffectiveNoOp_instance_;
1060 }
1061
1062 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000380) == 0x00000100) ) {
1063 return EffectiveNoOp_instance_;
1064 }
1065
1066 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000580) == 0x00000580) ) {
1067 return EffectiveNoOp_instance_;
1068 }
1069
1070 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000280) == 0x00000200) ) {
1071 return EffectiveNoOp_instance_;
1072 }
1073
1074 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000700) == 0x00000200) ) {
1075 return EffectiveNoOp_instance_;
1076 }
1077
1078 if (((insn & 0x00030000) == 0x00030000) && ((insn & 0x00000400) == 0x00000400) ) {
1079 return EffectiveNoOp_instance_;
1080 }
1081
1082 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000100) == 0x00000000) ) {
1083 return EffectiveNoOp_instance_;
1084 }
1085
1086 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000200) == 0x00000000) ) {
1087 return EffectiveNoOp_instance_;
1088 }
1089
1090 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000600) == 0x00000000) ) {
1091 return EffectiveNoOp_instance_;
1092 }
1093
1094 // Catch any attempt to fall through...
1095 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2misc could not parse %08X",
1096 insn.bits(31,0));
1097 return Forbidden_instance_;
1098 }
1099
1100
1101 /*
1102 * Implementation of table simd_dp_2scalar.
1103 * Specified by: ('See Section A7.4.3',)
1104 */
1105 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_2scalar(
1106 const nacl_arm_dec::Instruction insn) const {
1107 UNREFERENCED_PARAMETER(insn);
1108 if ((true) && (true)) {
1109 return Undefined_instance_;
1110 }
1111
1112 if (((insn & 0x00000B00) == 0x00000200) && (true)) {
1113 return EffectiveNoOp_instance_;
1114 }
1115
1116 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x01000000) == 0x00000000) ) {
1117 return EffectiveNoOp_instance_;
1118 }
1119
1120 if (((insn & 0x00000F00) == 0x00000A00) && (true)) {
1121 return EffectiveNoOp_instance_;
1122 }
1123
1124 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x01000000) == 0x00000000) ) {
1125 return EffectiveNoOp_instance_;
1126 }
1127
1128 if (((insn & 0x00000200) == 0x00000000) && (true)) {
1129 return EffectiveNoOp_instance_;
1130 }
1131
1132 // Catch any attempt to fall through...
1133 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2scalar could not parse %08X",
1134 insn.bits(31,0));
1135 return Forbidden_instance_;
1136 }
1137
1138
1139 /*
1140 * Implementation of table simd_dp_2shift.
1141 * Specified by: ('See Section A7.4.4',)
1142 */
1143 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_2shift(
1144 const nacl_arm_dec::Instruction insn) const {
1145 UNREFERENCED_PARAMETER(insn);
1146 if ((true) && (true) && (true) && (true)) {
1147 return Undefined_instance_;
1148 }
1149
1150 if (((insn & 0x00000F00) == 0x00000500) && ((insn & 0x01000000) == 0x00000000) && (true) && (true)) {
1151 return EffectiveNoOp_instance_;
1152 }
1153
1154 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x00000040) == 0x00000000) && ((insn & 0x00000080) == 0x00000000)) {
1155 return EffectiveNoOp_instance_;
1156 }
1157
1158 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00000040) == 0x00000000) && (true)) {
1159 return EffectiveNoOp_instance_;
1160 }
1161
1162 if (((insn & 0x00000F00) == 0x00000A00) && (true) && ((insn & 0x00000040) == 0 x00000000) && (true)) {
1163 return EffectiveNoOp_instance_;
1164 }
1165
1166 if (((insn & 0x00000E00) == 0x00000400) && ((insn & 0x01000000) == 0x01000000) && (true) && (true)) {
1167 return EffectiveNoOp_instance_;
1168 }
1169
1170 if (((insn & 0x00000600) == 0x00000600) && (true) && (true) && (true)) {
1171 return EffectiveNoOp_instance_;
1172 }
1173
1174 if (((insn & 0x00000F00) == 0x00000800) && (true) && ((insn & 0x00000040) == 0 x00000040) && (true)) {
1175 return EffectiveNoOp_instance_;
1176 }
1177
1178 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1179 return EffectiveNoOp_instance_;
1180 }
1181
1182 if (((insn & 0x00000C00) == 0x00000000) && (true) && (true) && (true)) {
1183 return EffectiveNoOp_instance_;
1184 }
1185
1186 // Catch any attempt to fall through...
1187 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2shift could not parse %08X",
1188 insn.bits(31,0));
1189 return Forbidden_instance_;
1190 }
1191
1192
1193 /*
1194 * Implementation of table simd_dp_3diff.
1195 * Specified by: ('See Section A7.4.2',)
1196 */
1197 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_3diff(
1198 const nacl_arm_dec::Instruction insn) const {
1199 UNREFERENCED_PARAMETER(insn);
1200 if ((true) && (true)) {
1201 return Undefined_instance_;
1202 }
1203
1204 if (((insn & 0x00000D00) == 0x00000900) && ((insn & 0x01000000) == 0x00000000) ) {
1205 return EffectiveNoOp_instance_;
1206 }
1207
1208 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x01000000) == 0x00000000) ) {
1209 return EffectiveNoOp_instance_;
1210 }
1211
1212 if (((insn & 0x00000900) == 0x00000800) && (true)) {
1213 return EffectiveNoOp_instance_;
1214 }
1215
1216 if (((insn & 0x00000800) == 0x00000000) && (true)) {
1217 return EffectiveNoOp_instance_;
1218 }
1219
1220 // Catch any attempt to fall through...
1221 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3diff could not parse %08X",
1222 insn.bits(31,0));
1223 return Forbidden_instance_;
1224 }
1225
1226
1227 /*
1228 * Implementation of table simd_dp_3same.
1229 * Specified by: ('See Section A7.4.1',)
1230 */
1231 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_dp_3same(
1232 const nacl_arm_dec::Instruction insn) const {
1233 UNREFERENCED_PARAMETER(insn);
1234 if ((true) && (true) && (true) && (true)) {
1235 return Undefined_instance_;
1236 }
1237
1238 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00000000)) {
1239 return EffectiveNoOp_instance_;
1240 }
1241
1242 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00200000)) {
1243 return EffectiveNoOp_instance_;
1244 }
1245
1246 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1247 return EffectiveNoOp_instance_;
1248 }
1249
1250 if (((insn & 0x00000D00) == 0x00000100) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1251 return EffectiveNoOp_instance_;
1252 }
1253
1254 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1255 return EffectiveNoOp_instance_;
1256 }
1257
1258 if (((insn & 0x00000F00) == 0x00000500) && (true) && (true) && (true)) {
1259 return EffectiveNoOp_instance_;
1260 }
1261
1262 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1263 return EffectiveNoOp_instance_;
1264 }
1265
1266 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1267 return EffectiveNoOp_instance_;
1268 }
1269
1270 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1271 return EffectiveNoOp_instance_;
1272 }
1273
1274 if (((insn & 0x00000F00) == 0x00000D00) && (true) && ((insn & 0x01000000) == 0 x00000000) && (true)) {
1275 return EffectiveNoOp_instance_;
1276 }
1277
1278 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && (true) && ((insn & 0x00200000) == 0x00000000)) {
1279 return EffectiveNoOp_instance_;
1280 }
1281
1282 if (((insn & 0x00000700) == 0x00000700) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1283 return EffectiveNoOp_instance_;
1284 }
1285
1286 if (((insn & 0x00000B00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x00000000) && (true)) {
1287 return EffectiveNoOp_instance_;
1288 }
1289
1290 if (((insn & 0x00000900) == 0x00000000) && (true) && (true) && (true)) {
1291 return EffectiveNoOp_instance_;
1292 }
1293
1294 if (((insn & 0x00000D00) == 0x00000800) && (true) && (true) && (true)) {
1295 return EffectiveNoOp_instance_;
1296 }
1297
1298 if (((insn & 0x00000F00) == 0x00000100) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1299 return EffectiveNoOp_instance_;
1300 }
1301
1302 // Catch any attempt to fall through...
1303 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3same could not parse %08X",
1304 insn.bits(31,0));
1305 return Forbidden_instance_;
1306 }
1307
1308
1309 /*
1310 * Implementation of table simd_load_store.
1311 * Specified by: ('See Section A7.7',)
1312 */
1313 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_load_store(
1314 const nacl_arm_dec::Instruction insn) const {
1315
1316 if (((insn & 0x00200000) == 0x00000000)) {
1317 return decode_simd_load_store_l0(insn);
1318 }
1319
1320 if (((insn & 0x00200000) == 0x00200000)) {
1321 return decode_simd_load_store_l1(insn);
1322 }
1323
1324 // Catch any attempt to fall through...
1325 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store could not parse %08X",
1326 insn.bits(31,0));
1327 return Forbidden_instance_;
1328 }
1329
1330
1331 /*
1332 * Implementation of table simd_load_store_l0.
1333 * Specified by: ('See Section A7.7, Table A7 - 20',)
1334 */
1335 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_load_store_l0(
1336 const nacl_arm_dec::Instruction insn) const {
1337 UNREFERENCED_PARAMETER(insn);
1338 if ((true) && (true)) {
1339 return Undefined_instance_;
1340 }
1341
1342 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1343 return VectorStore_instance_;
1344 }
1345
1346 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1347 return VectorStore_instance_;
1348 }
1349
1350 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1351 return VectorStore_instance_;
1352 }
1353
1354 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1355 return VectorStore_instance_;
1356 }
1357
1358 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000800) == 0x00000000) ) {
1359 return VectorStore_instance_;
1360 }
1361
1362 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000C00) == 0x00000800) ) {
1363 return VectorStore_instance_;
1364 }
1365
1366 // Catch any attempt to fall through...
1367 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l0 could not parse %08X" ,
1368 insn.bits(31,0));
1369 return Forbidden_instance_;
1370 }
1371
1372
1373 /*
1374 * Implementation of table simd_load_store_l1.
1375 * Specified by: ('See Section A7.7, Table A7 - 21',)
1376 */
1377 const NamedClassDecoder& NamedArm32DecoderState::decode_simd_load_store_l1(
1378 const nacl_arm_dec::Instruction insn) const {
1379 UNREFERENCED_PARAMETER(insn);
1380 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1381 return VectorLoad_instance_;
1382 }
1383
1384 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1385 return VectorLoad_instance_;
1386 }
1387
1388 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1389 return VectorLoad_instance_;
1390 }
1391
1392 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1393 return VectorLoad_instance_;
1394 }
1395
1396 if (((insn & 0x00800000) == 0x00800000) && (true)) {
1397 return VectorLoad_instance_;
1398 }
1399
1400 if ((true) && (true)) {
1401 return Undefined_instance_;
1402 }
1403
1404 // Catch any attempt to fall through...
1405 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l1 could not parse %08X" ,
1406 insn.bits(31,0));
1407 return Forbidden_instance_;
1408 }
1409
1410
1411 /*
1412 * Implementation of table super_cop.
1413 * Specified by: ('See Section A5.6',)
1414 */
1415 const NamedClassDecoder& NamedArm32DecoderState::decode_super_cop(
1416 const nacl_arm_dec::Instruction insn) const {
1417 UNREFERENCED_PARAMETER(insn);
1418 if (((insn & 0x03100000) == 0x02100000) && ((insn & 0x00000010) == 0x00000010) ) {
1419 return MoveFromCoprocessor_instance_;
1420 }
1421
1422 if (((insn & 0x02100000) == 0x00000000) && (true)) {
1423 return StoreCoprocessor_instance_;
1424 }
1425
1426 if (((insn & 0x03F00000) == 0x00400000) && (true)) {
1427 return CoprocessorOp_instance_;
1428 }
1429
1430 if (((insn & 0x03E00000) == 0x00000000) && (true)) {
1431 return Undefined_instance_;
1432 }
1433
1434 if (((insn & 0x02100000) == 0x00100000) && (true)) {
1435 return LoadCoprocessor_instance_;
1436 }
1437
1438 if (((insn & 0x03000000) == 0x02000000) && ((insn & 0x00000010) == 0x00000000) ) {
1439 return CoprocessorOp_instance_;
1440 }
1441
1442 if (((insn & 0x03100000) == 0x02000000) && ((insn & 0x00000010) == 0x00000010) ) {
1443 return CoprocessorOp_instance_;
1444 }
1445
1446 if (((insn & 0x03F00000) == 0x00500000) && (true)) {
1447 return MoveDoubleFromCoprocessor_instance_;
1448 }
1449
1450 if (((insn & 0x03000000) == 0x03000000) && (true)) {
1451 return Forbidden_instance_;
1452 }
1453
1454 // Catch any attempt to fall through...
1455 fprintf(stderr, "TABLE IS INCOMPLETE: super_cop could not parse %08X",
1456 insn.bits(31,0));
1457 return Forbidden_instance_;
1458 }
1459
579 1460
580 /* 1461 /*
581 * Implementation of table sync. 1462 * Implementation of table sync.
582 * Specified by: See Section A5.2.10. 1463 * Specified by: ('See Section A5.2.10',)
583 */ 1464 */
584 static inline const ClassDecoder &decode_sync( 1465 const NamedClassDecoder& NamedArm32DecoderState::decode_sync(
585 const Instruction insn, const NamedArm32DecoderState *state) { 1466 const nacl_arm_dec::Instruction insn) const {
1467 UNREFERENCED_PARAMETER(insn);
1468 if (((insn & 0x00B00000) == 0x00000000)) {
1469 return Deprecated_instance_;
1470 }
1471
1472 if (((insn & 0x00F00000) == 0x00B00000)) {
1473 return LoadDoubleExclusive_instance_;
1474 }
1475
1476 if ((true)) {
1477 return Undefined_instance_;
1478 }
1479
1480 if (((insn & 0x00F00000) == 0x00C00000)) {
1481 return StoreExclusive_instance_;
1482 }
1483
1484 if (((insn & 0x00B00000) == 0x00A00000)) {
1485 return StoreExclusive_instance_;
1486 }
1487
1488 if (((insn & 0x00F00000) == 0x00900000)) {
1489 return LoadExclusive_instance_;
1490 }
1491
586 if (((insn & 0x00F00000) == 0x00800000)) { 1492 if (((insn & 0x00F00000) == 0x00800000)) {
587 return state->StoreExclusive_instance_; 1493 return StoreExclusive_instance_;
588 } 1494 }
589 1495
590 if (((insn & 0x00F00000) == 0x00900000)) {
591 return state->LoadExclusive_instance_;
592 }
593
594 if (((insn & 0x00F00000) == 0x00B00000)) {
595 return state->LoadDoubleExclusive_instance_;
596 }
597
598 if (((insn & 0x00F00000) == 0x00C00000)) {
599 return state->StoreExclusive_instance_;
600 }
601
602 if (((insn & 0x00B00000) == 0x00000000)) {
603 return state->Deprecated_instance_;
604 }
605
606 if (((insn & 0x00B00000) == 0x00A00000)) {
607 return state->StoreExclusive_instance_;
608 }
609
610 if (((insn & 0x00D00000) == 0x00D00000)) { 1496 if (((insn & 0x00D00000) == 0x00D00000)) {
611 return state->LoadExclusive_instance_; 1497 return LoadExclusive_instance_;
612 } 1498 }
613 1499
614 if ((true)) { 1500 // Catch any attempt to fall through...
615 return state->Undefined_instance_; 1501 fprintf(stderr, "TABLE IS INCOMPLETE: sync could not parse %08X",
616 } 1502 insn.bits(31,0));
617 1503 return Forbidden_instance_;
618 // Catch any attempt to fall through... 1504 }
619 fprintf(stderr, "TABLE IS INCOMPLETE: sync could not parse %08X",insn.bits(31, 0)); 1505
620 return state->Forbidden_instance_; 1506
621 } 1507 /*
622 1508 * Implementation of table unconditional.
623 /* 1509 * Specified by: ('See Section A5.7',)
624 * Implementation of table msr_and_hints. 1510 */
625 * Specified by: See Section A5.2.11. 1511 const NamedClassDecoder& NamedArm32DecoderState::decode_unconditional(
626 */ 1512 const nacl_arm_dec::Instruction insn) const {
627 static inline const ClassDecoder &decode_msr_and_hints( 1513
628 const Instruction insn, const NamedArm32DecoderState *state) { 1514 if (((insn & 0x08000000) == 0x00000000) && (true) && (true)) {
629 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000000)) { 1515 return decode_misc_hints_simd(insn);
630 return state->EffectiveNoOp_instance_; 1516 }
631 } 1517
632 1518 if (((insn & 0x0F100000) == 0x0E100000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
633 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000002)) { 1519 return MoveFromCoprocessor_instance_;
634 return state->EffectiveNoOp_instance_; 1520 }
635 } 1521
636 1522 if (((insn & 0x0FB00000) == 0x0C300000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
637 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FF) == 0x00000004)) { 1523 return LoadCoprocessor_instance_;
638 return state->EffectiveNoOp_instance_; 1524 }
639 } 1525
640 1526 if (((insn & 0x0F900000) == 0x0C900000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
641 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000FD) == 0x00000001)) { 1527 return LoadCoprocessor_instance_;
642 return state->EffectiveNoOp_instance_; 1528 }
643 } 1529
644 1530 if (((insn & 0x0F100000) == 0x0D100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
645 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00000000) && ((insn & 0x000000F0) == 0x000000F0)) { 1531 return LoadCoprocessor_instance_;
646 return state->EffectiveNoOp_instance_; 1532 }
647 } 1533
648
649 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000F0000) == 0x00040000) && (true)) {
650 return state->MoveToStatusRegister_instance_;
651 }
652
653 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x000B0000) == 0x00080000) && (true)) {
654 return state->MoveToStatusRegister_instance_;
655 }
656
657 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00030000) == 0x00010000) && (true)) {
658 return state->Forbidden_instance_;
659 }
660
661 if (((insn & 0x00400000) == 0x00000000) && ((insn & 0x00020000) == 0x00020000) && (true)) {
662 return state->Forbidden_instance_;
663 }
664
665 if (((insn & 0x00400000) == 0x00400000) && (true) && (true)) {
666 return state->Forbidden_instance_;
667 }
668
669 if ((true) && (true) && (true)) { 1534 if ((true) && (true) && (true)) {
670 return state->Forbidden_instance_; 1535 return Undefined_instance_;
671 } 1536 }
672 1537
673 // Catch any attempt to fall through... 1538 if (((insn & 0x0FF00000) == 0x0C500000) && (true) && (true)) {
674 fprintf(stderr, "TABLE IS INCOMPLETE: msr_and_hints could not parse %08X",insn .bits(31,0)); 1539 return MoveDoubleFromCoprocessor_instance_;
675 return state->Forbidden_instance_; 1540 }
676 } 1541
677 1542 if (((insn & 0x0F000000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
678 /* 1543 return CoprocessorOp_instance_;
679 * Implementation of table misc. 1544 }
680 * Specified by: See Section A5.2.12. 1545
681 */ 1546 if (((insn & 0x0F100000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
682 static inline const ClassDecoder &decode_misc( 1547 return CoprocessorOp_instance_;
683 const Instruction insn, const NamedArm32DecoderState *state) { 1548 }
684 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00000000)) { 1549
685 return state->MoveToStatusRegister_instance_; 1550 if (((insn & 0x0FB00000) == 0x0C200000) && (true) && (true)) {
686 } 1551 return StoreCoprocessor_instance_;
687 1552 }
688 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00030000) == 0x00010000)) { 1553
689 return state->Forbidden_instance_; 1554 if (((insn & 0x0F900000) == 0x0C800000) && (true) && (true)) {
690 } 1555 return StoreCoprocessor_instance_;
691 1556 }
692 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00200000) && ((insn & 0x00020000) == 0x00020000)) { 1557
693 return state->Forbidden_instance_; 1558 if (((insn & 0x0F100000) == 0x0D000000) && (true) && (true)) {
694 } 1559 return StoreCoprocessor_instance_;
695 1560 }
696 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00600000) == 0x00600000) && (true)) { 1561
697 return state->Forbidden_instance_;
698 }
699
700 if (((insn & 0x00000070) == 0x00000000) && ((insn & 0x00200000) == 0x00000000) && (true)) {
701 return state->DataProc_instance_;
702 }
703
704 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00200000) && (true)) {
705 return state->BxBlx_instance_;
706 }
707
708 if (((insn & 0x00000070) == 0x00000010) && ((insn & 0x00600000) == 0x00600000) && (true)) {
709 return state->DataProc_instance_;
710 }
711
712 if (((insn & 0x00000070) == 0x00000020) && ((insn & 0x00600000) == 0x00200000) && (true)) {
713 return state->Forbidden_instance_;
714 }
715
716 if (((insn & 0x00000070) == 0x00000030) && ((insn & 0x00600000) == 0x00200000) && (true)) {
717 return state->BxBlx_instance_;
718 }
719
720 if (((insn & 0x00000070) == 0x00000050) && (true) && (true)) {
721 return decode_sat_add_sub(insn, state);
722 }
723
724 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00200000) && (true)) {
725 return state->Breakpoint_instance_;
726 }
727
728 if (((insn & 0x00000070) == 0x00000070) && ((insn & 0x00600000) == 0x00600000) && (true)) {
729 return state->Forbidden_instance_;
730 }
731
732 if ((true) && (true) && (true)) {
733 return state->Undefined_instance_;
734 }
735
736 // Catch any attempt to fall through...
737 fprintf(stderr, "TABLE IS INCOMPLETE: misc could not parse %08X",insn.bits(31, 0));
738 return state->Forbidden_instance_;
739 }
740
741 /*
742 * Implementation of table load_store_word_byte.
743 * Specified by: See Section A5.3.
744 */
745 static inline const ClassDecoder &decode_load_store_word_byte(
746 const Instruction insn, const NamedArm32DecoderState *state) {
747 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x01200000) == 0x00200000) && (true)) {
748 return state->Forbidden_instance_;
749 }
750
751 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00000000) && (true)) {
752 return state->StoreImmediate_instance_;
753 }
754
755 if (((insn & 0x02000000) == 0x00000000) && ((insn & 0x00100000) == 0x00100000) && (true)) {
756 return state->LoadImmediate_instance_;
757 }
758
759 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x01200000) == 0x00200000) && ((insn & 0x00000010) == 0x00000000)) {
760 return state->Forbidden_instance_;
761 }
762
763 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
764 return state->StoreRegister_instance_;
765 }
766
767 if (((insn & 0x02000000) == 0x02000000) && ((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000010) == 0x00000000)) {
768 return state->LoadRegister_instance_;
769 }
770
771 // Catch any attempt to fall through...
772 fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08 X",insn.bits(31,0));
773 return state->Forbidden_instance_;
774 }
775
776 /*
777 * Implementation of table media.
778 * Specified by: See Section A5.4.
779 */
780 static inline const ClassDecoder &decode_media(
781 const Instruction insn, const NamedArm32DecoderState *state) {
782 if (((insn & 0x01F00000) == 0x01800000) && ((insn & 0x000000E0) == 0x00000000) ) {
783 return state->Multiply_instance_;
784 }
785
786 if (((insn & 0x01F00000) == 0x01F00000) && ((insn & 0x000000E0) == 0x000000E0) ) {
787 return state->Roadblock_instance_;
788 }
789
790 if (((insn & 0x01E00000) == 0x01C00000) && ((insn & 0x00000060) == 0x00000000) ) {
791 return state->DataProc_instance_;
792 }
793
794 if (((insn & 0x01A00000) == 0x01A00000) && ((insn & 0x00000060) == 0x00000040) ) {
795 return state->DataProc_instance_;
796 }
797
798 if (((insn & 0x01800000) == 0x00000000) && (true)) {
799 return decode_parallel_add_sub(insn, state);
800 }
801
802 if (((insn & 0x01800000) == 0x00800000) && (true)) {
803 return decode_pack_sat_rev(insn, state);
804 }
805
806 if (((insn & 0x01800000) == 0x01000000) && (true)) {
807 return decode_signed_mult(insn, state);
808 }
809
810 if ((true) && (true)) {
811 return state->Undefined_instance_;
812 }
813
814 // Catch any attempt to fall through...
815 fprintf(stderr, "TABLE IS INCOMPLETE: media could not parse %08X",insn.bits(31 ,0));
816 return state->Forbidden_instance_;
817 }
818
819 /*
820 * Implementation of table parallel_add_sub.
821 * Specified by: See Sections A5.4.1, A5.4.2.
822 */
823 static inline const ClassDecoder &decode_parallel_add_sub(
824 const Instruction insn, const NamedArm32DecoderState *state) {
825 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000080) ) {
826 return state->DataProc_instance_;
827 }
828
829 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x000000E0) == 0x000000E0) ) {
830 return state->DataProc_instance_;
831 }
832
833 if (((insn & 0x00300000) == 0x00200000) && ((insn & 0x00000080) == 0x00000000) ) {
834 return state->DataProc_instance_;
835 }
836
837 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x00000080) ) {
838 return state->DataProc_instance_;
839 }
840
841 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x000000E0) == 0x000000E0) ) {
842 return state->DataProc_instance_;
843 }
844
845 if (((insn & 0x00100000) == 0x00100000) && ((insn & 0x00000080) == 0x00000000) ) {
846 return state->DataProc_instance_;
847 }
848
849 if ((true) && (true)) {
850 return state->Undefined_instance_;
851 }
852
853 // Catch any attempt to fall through...
854 fprintf(stderr, "TABLE IS INCOMPLETE: parallel_add_sub could not parse %08X",i nsn.bits(31,0));
855 return state->Forbidden_instance_;
856 }
857
858 /*
859 * Implementation of table pack_sat_rev.
860 * Specified by: See Section A5.4.3.
861 */
862 static inline const ClassDecoder &decode_pack_sat_rev(
863 const Instruction insn, const NamedArm32DecoderState *state) {
864 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000E0) == 0x000000A0) ) {
865 return state->PackSatRev_instance_;
866 }
867
868 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000020) == 0x00000000) ) {
869 return state->PackSatRev_instance_;
870 }
871
872 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x000000E0) == 0x00000060) ) {
873 return state->PackSatRev_instance_;
874 }
875
876 if (((insn & 0x00700000) == 0x00600000) && ((insn & 0x000000A0) == 0x00000020) ) {
877 return state->PackSatRev_instance_;
878 }
879
880 if (((insn & 0x00700000) == 0x00700000) && ((insn & 0x000000E0) == 0x00000020) ) {
881 return state->PackSatRev_instance_;
882 }
883
884 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x00000060) ) {
885 return state->PackSatRev_instance_;
886 }
887
888 if (((insn & 0x00300000) == 0x00300000) && ((insn & 0x000000E0) == 0x000000A0) ) {
889 return state->PackSatRev_instance_;
890 }
891
892 if (((insn & 0x00500000) == 0x00000000) && ((insn & 0x000000E0) == 0x00000060) ) {
893 return state->PackSatRev_instance_;
894 }
895
896 if (((insn & 0x00600000) == 0x00200000) && ((insn & 0x000000E0) == 0x00000020) ) {
897 return state->PackSatRev_instance_;
898 }
899
900 if (((insn & 0x00200000) == 0x00200000) && ((insn & 0x00000020) == 0x00000000) ) {
901 return state->PackSatRev_instance_;
902 }
903
904 if ((true) && (true)) {
905 return state->Undefined_instance_;
906 }
907
908 // Catch any attempt to fall through...
909 fprintf(stderr, "TABLE IS INCOMPLETE: pack_sat_rev could not parse %08X",insn. bits(31,0));
910 return state->Forbidden_instance_;
911 }
912
913 /*
914 * Implementation of table signed_mult.
915 * Specified by: See Section A5.4.4.
916 */
917 static inline const ClassDecoder &decode_signed_mult(
918 const Instruction insn, const NamedArm32DecoderState *state) {
919 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x000000C0) == 0x00000040) && ((insn & 0x0000F000) != 0x0000F000)) {
920 return state->Multiply_instance_;
921 }
922
923 if (((insn & 0x00700000) == 0x00000000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
924 return state->Multiply_instance_;
925 }
926
927 if (((insn & 0x00700000) == 0x00400000) && ((insn & 0x00000080) == 0x00000000) && (true)) {
928 return state->LongMultiply_instance_;
929 }
930
931 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x00000000) && (true)) {
932 return state->Multiply_instance_;
933 }
934
935 if (((insn & 0x00700000) == 0x00500000) && ((insn & 0x000000C0) == 0x000000C0) && (true)) {
936 return state->Multiply_instance_;
937 }
938
939 if ((true) && (true) && (true)) {
940 return state->Undefined_instance_;
941 }
942
943 // Catch any attempt to fall through...
944 fprintf(stderr, "TABLE IS INCOMPLETE: signed_mult could not parse %08X",insn.b its(31,0));
945 return state->Forbidden_instance_;
946 }
947
948 /*
949 * Implementation of table branch_block_xfer.
950 * Specified by: See Section A5.5.
951 */
952 static inline const ClassDecoder &decode_branch_block_xfer(
953 const Instruction insn, const NamedArm32DecoderState *state) {
954 if (((insn & 0x02500000) == 0x00000000)) {
955 return state->StoreImmediate_instance_;
956 }
957
958 if (((insn & 0x02500000) == 0x00100000)) {
959 return state->LoadMultiple_instance_;
960 }
961
962 if (((insn & 0x02400000) == 0x00400000)) {
963 return state->Forbidden_instance_;
964 }
965
966 if (((insn & 0x02000000) == 0x02000000)) {
967 return state->Branch_instance_;
968 }
969
970 // Catch any attempt to fall through...
971 fprintf(stderr, "TABLE IS INCOMPLETE: branch_block_xfer could not parse %08X", insn.bits(31,0));
972 return state->Forbidden_instance_;
973 }
974
975 /*
976 * Implementation of table super_cop.
977 * Specified by: See Section A5.6.
978 */
979 static inline const ClassDecoder &decode_super_cop(
980 const Instruction insn, const NamedArm32DecoderState *state) {
981 if (((insn & 0x03F00000) == 0x00400000) && (true)) {
982 return state->CoprocessorOp_instance_;
983 }
984
985 if (((insn & 0x03F00000) == 0x00500000) && (true)) {
986 return state->MoveDoubleFromCoprocessor_instance_;
987 }
988
989 if (((insn & 0x03E00000) == 0x00000000) && (true)) {
990 return state->Undefined_instance_;
991 }
992
993 if (((insn & 0x03100000) == 0x02000000) && ((insn & 0x00000010) == 0x00000010) ) {
994 return state->CoprocessorOp_instance_;
995 }
996
997 if (((insn & 0x03100000) == 0x02100000) && ((insn & 0x00000010) == 0x00000010) ) {
998 return state->MoveFromCoprocessor_instance_;
999 }
1000
1001 if (((insn & 0x02100000) == 0x00000000) && (true)) {
1002 return state->StoreCoprocessor_instance_;
1003 }
1004
1005 if (((insn & 0x02100000) == 0x00100000) && (true)) {
1006 return state->LoadCoprocessor_instance_;
1007 }
1008
1009 if (((insn & 0x03000000) == 0x02000000) && ((insn & 0x00000010) == 0x00000000) ) {
1010 return state->CoprocessorOp_instance_;
1011 }
1012
1013 if (((insn & 0x03000000) == 0x03000000) && (true)) {
1014 return state->Forbidden_instance_;
1015 }
1016
1017 // Catch any attempt to fall through...
1018 fprintf(stderr, "TABLE IS INCOMPLETE: super_cop could not parse %08X",insn.bit s(31,0));
1019 return state->Forbidden_instance_;
1020 }
1021
1022 /*
1023 * Implementation of table unconditional.
1024 * Specified by: See Section A5.7.
1025 */
1026 static inline const ClassDecoder &decode_unconditional(
1027 const Instruction insn, const NamedArm32DecoderState *state) {
1028 if (((insn & 0x0FF00000) == 0x0C400000) && (true) && (true)) { 1562 if (((insn & 0x0FF00000) == 0x0C400000) && (true) && (true)) {
1029 return state->CoprocessorOp_instance_; 1563 return CoprocessorOp_instance_;
1030 } 1564 }
1031 1565
1032 if (((insn & 0x0FF00000) == 0x0C500000) && (true) && (true)) { 1566 if (((insn & 0x0E500000) == 0x08400000) && (true) && (true)) {
1033 return state->MoveDoubleFromCoprocessor_instance_; 1567 return Forbidden_instance_;
1034 } 1568 }
1035 1569
1036 if (((insn & 0x0FB00000) == 0x0C200000) && (true) && (true)) {
1037 return state->StoreCoprocessor_instance_;
1038 }
1039
1040 if (((insn & 0x0FB00000) == 0x0C300000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
1041 return state->LoadCoprocessor_instance_;
1042 }
1043
1044 if (((insn & 0x0F900000) == 0x0C800000) && (true) && (true)) {
1045 return state->StoreCoprocessor_instance_;
1046 }
1047
1048 if (((insn & 0x0F900000) == 0x0C900000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
1049 return state->LoadCoprocessor_instance_;
1050 }
1051
1052 if (((insn & 0x0E500000) == 0x08100000) && (true) && (true)) { 1570 if (((insn & 0x0E500000) == 0x08100000) && (true) && (true)) {
1053 return state->Forbidden_instance_; 1571 return Forbidden_instance_;
1054 } 1572 }
1055 1573
1056 if (((insn & 0x0E500000) == 0x08400000) && (true) && (true)) {
1057 return state->Forbidden_instance_;
1058 }
1059
1060 if (((insn & 0x0F100000) == 0x0D000000) && (true) && (true)) {
1061 return state->StoreCoprocessor_instance_;
1062 }
1063
1064 if (((insn & 0x0F100000) == 0x0D100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
1065 return state->LoadCoprocessor_instance_;
1066 }
1067
1068 if (((insn & 0x0F100000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
1069 return state->CoprocessorOp_instance_;
1070 }
1071
1072 if (((insn & 0x0F100000) == 0x0E100000) && ((insn & 0x00000010) == 0x00000010) && (true)) {
1073 return state->MoveFromCoprocessor_instance_;
1074 }
1075
1076 if (((insn & 0x0F000000) == 0x0E000000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1077 return state->CoprocessorOp_instance_;
1078 }
1079
1080 if (((insn & 0x0E000000) == 0x0A000000) && (true) && (true)) { 1574 if (((insn & 0x0E000000) == 0x0A000000) && (true) && (true)) {
1081 return state->Forbidden_instance_; 1575 return Forbidden_instance_;
1082 } 1576 }
1083 1577
1084 if (((insn & 0x08000000) == 0x00000000) && (true) && (true)) { 1578 // Catch any attempt to fall through...
1085 return decode_misc_hints_simd(insn, state); 1579 fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",
1086 } 1580 insn.bits(31,0));
1087 1581 return Forbidden_instance_;
1088 if ((true) && (true) && (true)) { 1582 }
1089 return state->Undefined_instance_; 1583
1090 } 1584
1091 1585 const NamedClassDecoder& NamedArm32DecoderState::
1092 // Catch any attempt to fall through... 1586 decode_named(const nacl_arm_dec::Instruction insn) const {
1093 fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",insn .bits(31,0)); 1587 return decode_ARMv7(insn);
1094 return state->Forbidden_instance_; 1588 }
1095 } 1589
1096 1590 const nacl_arm_dec::ClassDecoder& NamedArm32DecoderState::
1097 /* 1591 decode(const nacl_arm_dec::Instruction insn) const {
1098 * Implementation of table misc_hints_simd. 1592 return decode_named(insn).named_decoder();
1099 * Specified by: See Section A5.7.1. 1593 }
1100 */ 1594
1101 static inline const ClassDecoder &decode_misc_hints_simd( 1595 } // namespace nacl_arm_test
1102 const Instruction insn, const NamedArm32DecoderState *state) {
1103 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x000000F0) == 0x00000000) && ((insn & 0x00010000) == 0x00010000)) {
1104 return state->Forbidden_instance_;
1105 }
1106
1107 if (((insn & 0x07F00000) == 0x01000000) && ((insn & 0x00000020) == 0x00000000) && ((insn & 0x00010000) == 0x00000000)) {
1108 return state->Forbidden_instance_;
1109 }
1110
1111 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000010) && (true)) {
1112 return state->EffectiveNoOp_instance_;
1113 }
1114
1115 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000F0) == 0x00000050) && (true)) {
1116 return state->EffectiveNoOp_instance_;
1117 }
1118
1119 if (((insn & 0x07F00000) == 0x05700000) && ((insn & 0x000000D0) == 0x00000040) && (true)) {
1120 return state->EffectiveNoOp_instance_;
1121 }
1122
1123 if (((insn & 0x07700000) == 0x04100000) && (true) && (true)) {
1124 return state->EffectiveNoOp_instance_;
1125 }
1126
1127 if (((insn & 0x07700000) == 0x04500000) && (true) && (true)) {
1128 return state->EffectiveNoOp_instance_;
1129 }
1130
1131 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) != 0 x000F0000)) {
1132 return state->EffectiveNoOp_instance_;
1133 }
1134
1135 if (((insn & 0x07700000) == 0x05100000) && (true) && ((insn & 0x000F0000) == 0 x000F0000)) {
1136 return state->Unpredictable_instance_;
1137 }
1138
1139 if (((insn & 0x07700000) == 0x05500000) && (true) && (true)) {
1140 return state->EffectiveNoOp_instance_;
1141 }
1142
1143 if (((insn & 0x07700000) == 0x06500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1144 return state->EffectiveNoOp_instance_;
1145 }
1146
1147 if (((insn & 0x07700000) == 0x07500000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1148 return state->EffectiveNoOp_instance_;
1149 }
1150
1151 if (((insn & 0x06700000) == 0x06100000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1152 return state->EffectiveNoOp_instance_;
1153 }
1154
1155 if (((insn & 0x06300000) == 0x04300000) && (true) && (true)) {
1156 return state->Unpredictable_instance_;
1157 }
1158
1159 if (((insn & 0x06300000) == 0x06300000) && ((insn & 0x00000010) == 0x00000000) && (true)) {
1160 return state->Unpredictable_instance_;
1161 }
1162
1163 if (((insn & 0x07100000) == 0x04000000) && (true) && (true)) {
1164 return decode_simd_load_store(insn, state);
1165 }
1166
1167 if (((insn & 0x06000000) == 0x02000000) && (true) && (true)) {
1168 return decode_simd_dp(insn, state);
1169 }
1170
1171 if ((true) && (true) && (true)) {
1172 return state->Undefined_instance_;
1173 }
1174
1175 // Catch any attempt to fall through...
1176 fprintf(stderr, "TABLE IS INCOMPLETE: misc_hints_simd could not parse %08X",in sn.bits(31,0));
1177 return state->Forbidden_instance_;
1178 }
1179
1180 /*
1181 * Implementation of table simd_dp.
1182 * Specified by: See Section A7.4.
1183 */
1184 static inline const ClassDecoder &decode_simd_dp(
1185 const Instruction insn, const NamedArm32DecoderState *state) {
1186 if (((insn & 0x01000000) == 0x00000000) && ((insn & 0x00B00000) == 0x00B00000) && (true) && ((insn & 0x00000010) == 0x00000000)) {
1187 return state->EffectiveNoOp_instance_;
1188 }
1189
1190 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000F00) == 0x00000C00) && ((insn & 0x00000090) == 0x00000000)) {
1191 return state->EffectiveNoOp_instance_;
1192 }
1193
1194 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000C00) == 0x00000800) && ((insn & 0x00000010) == 0x00000000)) {
1195 return state->EffectiveNoOp_instance_;
1196 }
1197
1198 if (((insn & 0x01000000) == 0x01000000) && ((insn & 0x00B00000) == 0x00B00000) && ((insn & 0x00000800) == 0x00000000) && ((insn & 0x00000010) == 0x00000000)) {
1199 return decode_simd_dp_2misc(insn, state);
1200 }
1201
1202 if ((true) && ((insn & 0x00B80000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1203 return decode_simd_dp_1imm(insn, state);
1204 }
1205
1206 if ((true) && ((insn & 0x00B80000) == 0x00880000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1207 return decode_simd_dp_2shift(insn, state);
1208 }
1209
1210 if ((true) && ((insn & 0x00B00000) == 0x00900000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1211 return decode_simd_dp_2shift(insn, state);
1212 }
1213
1214 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
1215 return decode_simd_dp_3diff(insn, state);
1216 }
1217
1218 if ((true) && ((insn & 0x00B00000) == 0x00A00000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
1219 return decode_simd_dp_2scalar(insn, state);
1220 }
1221
1222 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000000)) {
1223 return decode_simd_dp_3diff(insn, state);
1224 }
1225
1226 if ((true) && ((insn & 0x00A00000) == 0x00800000) && (true) && ((insn & 0x0000 0050) == 0x00000040)) {
1227 return decode_simd_dp_2scalar(insn, state);
1228 }
1229
1230 if ((true) && ((insn & 0x00A00000) == 0x00A00000) && (true) && ((insn & 0x0000 0090) == 0x00000010)) {
1231 return decode_simd_dp_2shift(insn, state);
1232 }
1233
1234 if ((true) && ((insn & 0x00800000) == 0x00000000) && (true) && (true)) {
1235 return decode_simd_dp_3same(insn, state);
1236 }
1237
1238 if ((true) && ((insn & 0x00800000) == 0x00800000) && (true) && ((insn & 0x0000 0090) == 0x00000090)) {
1239 return decode_simd_dp_2shift(insn, state);
1240 }
1241
1242 if ((true) && (true) && (true) && (true)) {
1243 return state->Undefined_instance_;
1244 }
1245
1246 // Catch any attempt to fall through...
1247 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp could not parse %08X",insn.bits( 31,0));
1248 return state->Forbidden_instance_;
1249 }
1250
1251 /*
1252 * Implementation of table simd_dp_3same.
1253 * Specified by: See Section A7.4.1.
1254 */
1255 static inline const ClassDecoder &decode_simd_dp_3same(
1256 const Instruction insn, const NamedArm32DecoderState *state) {
1257 if (((insn & 0x00000F00) == 0x00000100) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1258 return state->EffectiveNoOp_instance_;
1259 }
1260
1261 if (((insn & 0x00000F00) == 0x00000500) && (true) && (true) && (true)) {
1262 return state->EffectiveNoOp_instance_;
1263 }
1264
1265 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1266 return state->EffectiveNoOp_instance_;
1267 }
1268
1269 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1270 return state->EffectiveNoOp_instance_;
1271 }
1272
1273 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1274 return state->EffectiveNoOp_instance_;
1275 }
1276
1277 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00000000)) {
1278 return state->EffectiveNoOp_instance_;
1279 }
1280
1281 if (((insn & 0x00000F00) == 0x00000D00) && (true) && ((insn & 0x01000000) == 0 x00000000) && (true)) {
1282 return state->EffectiveNoOp_instance_;
1283 }
1284
1285 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00200000) == 0x00200000)) {
1286 return state->EffectiveNoOp_instance_;
1287 }
1288
1289 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000000) && (true) && ((insn & 0x00200000) == 0x00000000)) {
1290 return state->EffectiveNoOp_instance_;
1291 }
1292
1293 if (((insn & 0x00000F00) == 0x00000E00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x01000000) && (true)) {
1294 return state->EffectiveNoOp_instance_;
1295 }
1296
1297 if (((insn & 0x00000700) == 0x00000700) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1298 return state->EffectiveNoOp_instance_;
1299 }
1300
1301 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x00000010) == 0x00000010) && (true) && (true)) {
1302 return state->EffectiveNoOp_instance_;
1303 }
1304
1305 if (((insn & 0x00000B00) == 0x00000B00) && ((insn & 0x00000010) == 0x00000010) && ((insn & 0x01000000) == 0x00000000) && (true)) {
1306 return state->EffectiveNoOp_instance_;
1307 }
1308
1309 if (((insn & 0x00000D00) == 0x00000100) && ((insn & 0x00000010) == 0x00000000) && (true) && (true)) {
1310 return state->EffectiveNoOp_instance_;
1311 }
1312
1313 if (((insn & 0x00000D00) == 0x00000800) && (true) && (true) && (true)) {
1314 return state->EffectiveNoOp_instance_;
1315 }
1316
1317 if (((insn & 0x00000900) == 0x00000000) && (true) && (true) && (true)) {
1318 return state->EffectiveNoOp_instance_;
1319 }
1320
1321 if ((true) && (true) && (true) && (true)) {
1322 return state->Undefined_instance_;
1323 }
1324
1325 // Catch any attempt to fall through...
1326 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3same could not parse %08X",insn .bits(31,0));
1327 return state->Forbidden_instance_;
1328 }
1329
1330 /*
1331 * Implementation of table simd_dp_3diff.
1332 * Specified by: See Section A7.4.2.
1333 */
1334 static inline const ClassDecoder &decode_simd_dp_3diff(
1335 const Instruction insn, const NamedArm32DecoderState *state) {
1336 if (((insn & 0x00000F00) == 0x00000D00) && ((insn & 0x01000000) == 0x00000000) ) {
1337 return state->EffectiveNoOp_instance_;
1338 }
1339
1340 if (((insn & 0x00000D00) == 0x00000900) && ((insn & 0x01000000) == 0x00000000) ) {
1341 return state->EffectiveNoOp_instance_;
1342 }
1343
1344 if (((insn & 0x00000900) == 0x00000800) && (true)) {
1345 return state->EffectiveNoOp_instance_;
1346 }
1347
1348 if (((insn & 0x00000800) == 0x00000000) && (true)) {
1349 return state->EffectiveNoOp_instance_;
1350 }
1351
1352 if ((true) && (true)) {
1353 return state->Undefined_instance_;
1354 }
1355
1356 // Catch any attempt to fall through...
1357 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_3diff could not parse %08X",insn .bits(31,0));
1358 return state->Forbidden_instance_;
1359 }
1360
1361 /*
1362 * Implementation of table simd_dp_2scalar.
1363 * Specified by: See Section A7.4.3.
1364 */
1365 static inline const ClassDecoder &decode_simd_dp_2scalar(
1366 const Instruction insn, const NamedArm32DecoderState *state) {
1367 if (((insn & 0x00000F00) == 0x00000A00) && (true)) {
1368 return state->EffectiveNoOp_instance_;
1369 }
1370
1371 if (((insn & 0x00000F00) == 0x00000B00) && ((insn & 0x01000000) == 0x00000000) ) {
1372 return state->EffectiveNoOp_instance_;
1373 }
1374
1375 if (((insn & 0x00000B00) == 0x00000200) && (true)) {
1376 return state->EffectiveNoOp_instance_;
1377 }
1378
1379 if (((insn & 0x00000B00) == 0x00000300) && ((insn & 0x01000000) == 0x00000000) ) {
1380 return state->EffectiveNoOp_instance_;
1381 }
1382
1383 if (((insn & 0x00000200) == 0x00000000) && (true)) {
1384 return state->EffectiveNoOp_instance_;
1385 }
1386
1387 if ((true) && (true)) {
1388 return state->Undefined_instance_;
1389 }
1390
1391 // Catch any attempt to fall through...
1392 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2scalar could not parse %08X",in sn.bits(31,0));
1393 return state->Forbidden_instance_;
1394 }
1395
1396 /*
1397 * Implementation of table simd_dp_2shift.
1398 * Specified by: See Section A7.4.4.
1399 */
1400 static inline const ClassDecoder &decode_simd_dp_2shift(
1401 const Instruction insn, const NamedArm32DecoderState *state) {
1402 if (((insn & 0x00000F00) == 0x00000500) && ((insn & 0x01000000) == 0x00000000) && (true) && (true)) {
1403 return state->EffectiveNoOp_instance_;
1404 }
1405
1406 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x00000000) && ((insn & 0x00000040) == 0x00000000) && ((insn & 0x00000080) == 0x00000000)) {
1407 return state->EffectiveNoOp_instance_;
1408 }
1409
1410 if (((insn & 0x00000F00) == 0x00000800) && ((insn & 0x01000000) == 0x01000000) && ((insn & 0x00000040) == 0x00000000) && (true)) {
1411 return state->EffectiveNoOp_instance_;
1412 }
1413
1414 if (((insn & 0x00000F00) == 0x00000800) && (true) && ((insn & 0x00000040) == 0 x00000040) && (true)) {
1415 return state->EffectiveNoOp_instance_;
1416 }
1417
1418 if (((insn & 0x00000F00) == 0x00000900) && (true) && (true) && (true)) {
1419 return state->EffectiveNoOp_instance_;
1420 }
1421
1422 if (((insn & 0x00000F00) == 0x00000A00) && (true) && ((insn & 0x00000040) == 0 x00000000) && (true)) {
1423 return state->EffectiveNoOp_instance_;
1424 }
1425
1426 if (((insn & 0x00000E00) == 0x00000400) && ((insn & 0x01000000) == 0x01000000) && (true) && (true)) {
1427 return state->EffectiveNoOp_instance_;
1428 }
1429
1430 if (((insn & 0x00000600) == 0x00000600) && (true) && (true) && (true)) {
1431 return state->EffectiveNoOp_instance_;
1432 }
1433
1434 if (((insn & 0x00000C00) == 0x00000000) && (true) && (true) && (true)) {
1435 return state->EffectiveNoOp_instance_;
1436 }
1437
1438 if ((true) && (true) && (true) && (true)) {
1439 return state->Undefined_instance_;
1440 }
1441
1442 // Catch any attempt to fall through...
1443 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2shift could not parse %08X",ins n.bits(31,0));
1444 return state->Forbidden_instance_;
1445 }
1446
1447 /*
1448 * Implementation of table simd_dp_2misc.
1449 * Specified by: See Section A7.4.5.
1450 */
1451 static inline const ClassDecoder &decode_simd_dp_2misc(
1452 const Instruction insn, const NamedArm32DecoderState *state) {
1453 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000780) == 0x00000700) ) {
1454 return state->EffectiveNoOp_instance_;
1455 }
1456
1457 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000380) == 0x00000100) ) {
1458 return state->EffectiveNoOp_instance_;
1459 }
1460
1461 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000580) == 0x00000580) ) {
1462 return state->EffectiveNoOp_instance_;
1463 }
1464
1465 if (((insn & 0x00030000) == 0x00000000) && ((insn & 0x00000100) == 0x00000000) ) {
1466 return state->EffectiveNoOp_instance_;
1467 }
1468
1469 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000380) == 0x00000380) ) {
1470 return state->EffectiveNoOp_instance_;
1471 }
1472
1473 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000280) == 0x00000200) ) {
1474 return state->EffectiveNoOp_instance_;
1475 }
1476
1477 if (((insn & 0x00030000) == 0x00010000) && ((insn & 0x00000200) == 0x00000000) ) {
1478 return state->EffectiveNoOp_instance_;
1479 }
1480
1481 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000007C0) == 0x00000300) ) {
1482 return state->EffectiveNoOp_instance_;
1483 }
1484
1485 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x000006C0) == 0x00000600) ) {
1486 return state->EffectiveNoOp_instance_;
1487 }
1488
1489 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000700) == 0x00000200) ) {
1490 return state->EffectiveNoOp_instance_;
1491 }
1492
1493 if (((insn & 0x00030000) == 0x00020000) && ((insn & 0x00000600) == 0x00000000) ) {
1494 return state->EffectiveNoOp_instance_;
1495 }
1496
1497 if (((insn & 0x00030000) == 0x00030000) && ((insn & 0x00000400) == 0x00000400) ) {
1498 return state->EffectiveNoOp_instance_;
1499 }
1500
1501 if ((true) && (true)) {
1502 return state->Undefined_instance_;
1503 }
1504
1505 // Catch any attempt to fall through...
1506 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_2misc could not parse %08X",insn .bits(31,0));
1507 return state->Forbidden_instance_;
1508 }
1509
1510 /*
1511 * Implementation of table simd_dp_1imm.
1512 * Specified by: See Section A7.4.6.
1513 */
1514 static inline const ClassDecoder &decode_simd_dp_1imm(
1515 const Instruction insn, const NamedArm32DecoderState *state) {
1516 if (((insn & 0x00000020) == 0x00000000) && (true)) {
1517 return state->EffectiveNoOp_instance_;
1518 }
1519
1520 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000E00) ) {
1521 return state->EffectiveNoOp_instance_;
1522 }
1523
1524 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000F00) == 0x00000F00) ) {
1525 return state->Undefined_instance_;
1526 }
1527
1528 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000E00) == 0x00000C00) ) {
1529 return state->EffectiveNoOp_instance_;
1530 }
1531
1532 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000C00) == 0x00000800) ) {
1533 return state->EffectiveNoOp_instance_;
1534 }
1535
1536 if (((insn & 0x00000020) == 0x00000020) && ((insn & 0x00000800) == 0x00000000) ) {
1537 return state->EffectiveNoOp_instance_;
1538 }
1539
1540 // Catch any attempt to fall through...
1541 fprintf(stderr, "TABLE IS INCOMPLETE: simd_dp_1imm could not parse %08X",insn. bits(31,0));
1542 return state->Forbidden_instance_;
1543 }
1544
1545 /*
1546 * Implementation of table simd_load_store.
1547 * Specified by: See Section A7.7.
1548 */
1549 static inline const ClassDecoder &decode_simd_load_store(
1550 const Instruction insn, const NamedArm32DecoderState *state) {
1551 if (((insn & 0x00200000) == 0x00000000)) {
1552 return decode_simd_load_store_l0(insn, state);
1553 }
1554
1555 if (((insn & 0x00200000) == 0x00200000)) {
1556 return decode_simd_load_store_l1(insn, state);
1557 }
1558
1559 // Catch any attempt to fall through...
1560 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store could not parse %08X",in sn.bits(31,0));
1561 return state->Forbidden_instance_;
1562 }
1563
1564 /*
1565 * Implementation of table simd_load_store_l0.
1566 * Specified by: See Section A7.7, Table A7-20.
1567 */
1568 static inline const ClassDecoder &decode_simd_load_store_l0(
1569 const Instruction insn, const NamedArm32DecoderState *state) {
1570 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1571 return state->VectorStore_instance_;
1572 }
1573
1574 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1575 return state->VectorStore_instance_;
1576 }
1577
1578 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1579 return state->VectorStore_instance_;
1580 }
1581
1582 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1583 return state->VectorStore_instance_;
1584 }
1585
1586 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000C00) == 0x00000800) ) {
1587 return state->VectorStore_instance_;
1588 }
1589
1590 if (((insn & 0x00800000) == 0x00800000) && ((insn & 0x00000800) == 0x00000000) ) {
1591 return state->VectorStore_instance_;
1592 }
1593
1594 if ((true) && (true)) {
1595 return state->Undefined_instance_;
1596 }
1597
1598 // Catch any attempt to fall through...
1599 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l0 could not parse %08X" ,insn.bits(31,0));
1600 return state->Forbidden_instance_;
1601 }
1602
1603 /*
1604 * Implementation of table simd_load_store_l1.
1605 * Specified by: See Section A7.7, Table A7-21.
1606 */
1607 static inline const ClassDecoder &decode_simd_load_store_l1(
1608 const Instruction insn, const NamedArm32DecoderState *state) {
1609 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000F00) == 0x00000300) ) {
1610 return state->VectorLoad_instance_;
1611 }
1612
1613 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000700) == 0x00000200) ) {
1614 return state->VectorLoad_instance_;
1615 }
1616
1617 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000600) == 0x00000000) ) {
1618 return state->VectorLoad_instance_;
1619 }
1620
1621 if (((insn & 0x00800000) == 0x00000000) && ((insn & 0x00000C00) == 0x00000400) ) {
1622 return state->VectorLoad_instance_;
1623 }
1624
1625 if (((insn & 0x00800000) == 0x00800000) && (true)) {
1626 return state->VectorLoad_instance_;
1627 }
1628
1629 if ((true) && (true)) {
1630 return state->Undefined_instance_;
1631 }
1632
1633 // Catch any attempt to fall through...
1634 fprintf(stderr, "TABLE IS INCOMPLETE: simd_load_store_l1 could not parse %08X" ,insn.bits(31,0));
1635 return state->Forbidden_instance_;
1636 }
1637
1638 NamedArm32DecoderState::NamedArm32DecoderState() :
1639 DecoderState()
1640 , CoprocessorOp_instance_()
1641 , ImmediateBic_instance_()
1642 , LoadMultiple_instance_()
1643 , LoadCoprocessor_instance_()
1644 , LoadDoubleExclusive_instance_()
1645 , Branch_instance_()
1646 , Test_instance_()
1647 , StoreRegister_instance_()
1648 , MoveDoubleFromCoprocessor_instance_()
1649 , TestImmediate_instance_()
1650 , BxBlx_instance_()
1651 , EffectiveNoOp_instance_()
1652 , LongMultiply_instance_()
1653 , Binary4RegisterShiftedOp_instance_()
1654 , Breakpoint_instance_()
1655 , Multiply_instance_()
1656 , PackSatRev_instance_()
1657 , LoadExclusive_instance_()
1658 , VectorStore_instance_()
1659 , Unary3RegisterShiftedOp_instance_()
1660 , Undefined_instance_()
1661 , DataProc_instance_()
1662 , Deprecated_instance_()
1663 , LoadImmediate_instance_()
1664 , StoreCoprocessor_instance_()
1665 , Roadblock_instance_()
1666 , LoadDoubleR_instance_()
1667 , StoreExclusive_instance_()
1668 , StoreImmediate_instance_()
1669 , MoveFromCoprocessor_instance_()
1670 , LoadRegister_instance_()
1671 , LoadDoubleI_instance_()
1672 , Binary3RegisterShiftedTest_instance_()
1673 , Unpredictable_instance_()
1674 , Forbidden_instance_()
1675 , VectorLoad_instance_()
1676 , MoveToStatusRegister_instance_()
1677 , SatAddSub_instance_()
1678 {
1679 }
1680
1681 NamedArm32DecoderState::~NamedArm32DecoderState() {
1682 }
1683
1684 const ClassDecoder &NamedArm32DecoderState::decode(const Instruction insn) const {
1685 return decode_ARMv7(insn, this);
1686 }
1687
1688 } // namespace
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