| OLD | NEW |
|---|
| 1 # ARMv7 Instruction Encodings | 1 # ARMv7 Instruction Encodings |
| 2 # | 2 # |
| 3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A | 3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A |
| 4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. | 4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. |
| 5 # Reproduction for purposes other than the development and distribution of | 5 # Reproduction for purposes other than the development and distribution of |
| 6 # Native Client may require the explicit permission of ARM Limited. | 6 # Native Client may require the explicit permission of ARM Limited. |
| 7 | 7 |
| 8 # This file defines the Native Client "instruction classes" assigned to every | 8 # This file defines the Native Client "instruction classes" assigned to every |
| 9 # possible ARMv7 instruction encoding. It is organized into a series of tables, | 9 # possible ARMv7 instruction encoding. It is organized into a series of tables, |
| 10 # and directly parallels the ARM Architecture Reference Manual cited above. | 10 # and directly parallels the ARM Architecture Reference Manual cited above. |
| 11 # | 11 # |
| 12 # Each table consists of | 12 # Each table consists of |
| 13 # - A name, | 13 # - A name, |
| 14 # - A citation in the Architecture Reference Manual, | 14 # - A citation in the Architecture Reference Manual, |
| 15 # - One or more columns defining bitfields to match, and | 15 # - One or more columns defining bitfields to match, and |
| 16 # - One or more rows describing patterns in those bitfields. | 16 # - One or more rows describing patterns in those bitfields. |
| 17 # | 17 # |
| 18 # A leading tilde (~) negates a pattern. A hyphen (-) is short for a string of | 18 # A leading tilde (~) negates a pattern. A hyphen (-) is short for a string of |
| 19 # don't-care bits (x). A double-quote (") indicates that a pattern is the same | 19 # don't-care bits (x). A double-quote (") indicates that a pattern is the same |
| 20 # as the row above it. | 20 # as the row above it. |
| 21 # | 21 # |
| 22 # Each row may specify a terminal instruction class ("=InstClass"), or forward | 22 # Each row may specify a terminal instruction class ("=InstClass"), or forward |
| 23 # the reader to a different table ("->table_name"). | 23 # the reader to a different table ("->table_name"). |
| 24 # | 24 # |
| 25 # If an encoding is not valid in every ARM architecture rev, the instruction | 25 # If an encoding is not valid in every ARM architecture rev, the instruction |
| 26 # class may indicate the rev or feature that makes the encoding valid in | 26 # class may indicate the rev or feature that makes the encoding valid in |
| 27 # parentheses. | 27 # parentheses. |
| 28 | 28 # |
| 29 -- ARMv7 (See Section A5.1) | 29 # For documentation and testing, an "=InstClass" can be followed by up to 3 |
| 30 cond(31:28) op1(27:25) op(4) | 30 # additional identifiers, and has the form: |
| 31 ~1111 00x - ->dp_misc | 31 # =InstClass Rule Pattern Constraints |
| 32 " 010 - ->load_store_word_byte | 32 # where |
| 33 " 011 0 ->load_store_word_byte | 33 # InstClass - is the class decoder to return when matched. |
| 34 " " 1 ->media | 34 # Rule - is the Arm rule that applies to the match (see below). |
| 35 " 10x - ->branch_block_xfer | 35 # Pattern - is a bitpattern for testing instances of the rule. |
| 36 " 11x - ->super_cop | 36 # Constraints - identifies what additional constraints are assumed |
| 37 1111 - - ->unconditional | 37 # by the corresponding rule. |
| 38 | 38 # |
| 39 -- dp_misc (See Section A5.2) | 39 # The Rules are identified with an identifier of the form: |
| 40 op(25) op1(24:20) op2(7:4) | 40 # NNN_Rule_SS_AA_Pppp |
| 41 0 ~10xx0 xxx0 ->dp_reg | 41 # where |
| 42 " " 0xx1 ->dp_reg_shifted | 42 # NNN is the nmenonic of the instruction. |
| 43 " 10xx0 0xxx ->misc | 43 # SS is the section number in A8.6.SS that define the instruction. |
| 44 " " 1xx0 ->half_mult | 44 # AA is the instruction form on that page, |
| 45 " 0xxxx 1001 ->mult | 45 # pp is the page number in A8-pp that the instruction is on. |
| 46 " 1xxxx 1001 ->sync | 46 # |
| 47 " ~0xx1x 1011 ->extra_load_store | 47 # Patterns are sequences of 32 characters as follows: |
| 48 " " 11x1 " | 48 # '1' - Bit must be value 1. |
| 49 " 0xx1x 1011 =Forbidden # Load/Store Unprivileged, plus undef | 49 # '0' - Bit must be value 0. |
| 50 " " 11x1 " | 50 # 'aaa...aa' (for some sequence of m lower case letters) - |
| 51 1 ~10xx0 - ->dp_immed | 51 # Try all possible combinations of bits for the m bytes. |
| 52 " 10000 - =DataProc(v6T2) # MOV (immediate) 16-bit version | 52 # 'AAA...A' (for some sequence of m upper case letters) - |
| 53 " 10100 - =DataProc(v6T2) # MOVT | 53 # Try the following combinations: |
| 54 " 10x10 - ->msr_and_hints | 54 # (1) All m bits set to 1. |
| 55 | 55 # (2) All m bits set to 0. |
| 56 -- dp_reg (See Section A5.2.1) | 56 # (3) For each 4-bit subsequence, try all combinations, |
| 57 op1(24:20) op2(11:7) op3(6:5) | 57 # setting remaining bits to 1. |
| 58 0000x - - =DataProc # AND(register) A8-36 | 58 # (4) For each 4-bit subsequence, try all combinations, |
| 59 0001x - - =DataProc # EOR(register) A8-96 | 59 # setting remaining bits to 0. |
| 60 0010x - - =DataProc # SUB(register) A8-422 | 60 # |
| 61 0011x - - =DataProc # RSB(register) A8-286 | 61 # Constraints identifiers used are: |
| 62 0100x - - =DataProc # ADD(register) A8-24 | 62 # RegsNotPc - All register defined by instruction are not Pc (R15). |
| 63 0101x - - =DataProc # ADC(register) A8-16 | 63 |
| 64 0110x - - =DataProc # SBC(register) A8-304 | 64 +-- ARMv7 (See Section A5.1) |
| 65 0111x - - =DataProc # RSC(register) A8-292 | 65 | cond(31:28) op1(27:25) op(4) |
| 66 10001 - - =Test # TST(register) A8-456 | 66 | ~1111 00x - ->dp_misc |
| 67 10011 - - =Test # TEQ(register) A8-450 | 67 | " 010 - ->load_store_word_byte |
| 68 10101 - - =Test # CMP(register) A8-82 | 68 | " 011 0 ->load_store_word_byte |
| 69 10111 - - =Test # CMN(register) A8-76 | 69 | " " 1 ->media |
| 70 1100x - - =DataProc # ORR(register) A8-230 | 70 | " 10x - ->branch_block_xfer |
| 71 1101x 00000 00 =DataProc # MOV(register) A8-196 | 71 | " 11x - ->super_cop |
| 72 " ~00000 00 =DataProc # LSL(immediate) A8-178 | 72 | 1111 - - ->unconditional |
| 73 " - 01 =DataProc # LSR(immediate) A8-182 | 73 +-- |
| 74 " - 10 =DataProc # ASR(immediate) A8-40 | 74 |
| 75 " 00000 11 =DataProc # RRX A8-282 | 75 +-- dp_misc (See Section A5.2) |
| 76 " ~00000 11 =DataProc # ROR(immediate) A8-278 | 76 | op(25) op1(24:20) op2(7:4) |
| 77 1110x - - =DataProc # BIC(register) A8-52 | 77 | 0 ~10xx0 xxx0 ->dp_reg |
| 78 1111x - - =DataProc # MVN(register) A8-216 | 78 | " " 0xx1 ->dp_reg_shifted |
| 79 | 79 | " 10xx0 0xxx ->misc |
| 80 -- dp_reg_shifted (See Section A5.2.2) | 80 | " " 1xx0 ->half_mult |
| 81 op1(24:20) op2(6:5) | 81 | " 0xxxx 1001 ->mult |
| 82 0000x - =Binary4RegisterShiftedOp # AND(register-shifted) A1 A8-3
8 | 82 | " 1xxxx 1001 ->sync |
| 83 0001x - =Binary4RegisterShiftedOp # EOR(register-shifted) A1 A8-9
8 | 83 | " ~0xx1x 1011 ->extra_load_store |
| 84 0010x - =Binary4RegisterShiftedOp # SUB(register-shifted) A1 A8-4
24 | 84 | " " 11x1 " |
| 85 0011x - =Binary4RegisterShiftedOp # RSB(register-shifted) A1 A8-2
88 | 85 | " 0xx1x 1011 =Forbidden # Load/Store Unprivileged, plus undef |
| 86 0100x - =Binary4RegisterShiftedOp # ADD(register-shifted) A1 A8-2
6 | 86 | " " 11x1 " |
| 87 0101x - =Binary4RegisterShiftedOp # ADC(register-shifted) A1 A8-1
8 | 87 | 1 ~10xx0 - ->dp_immed |
| 88 0110x - =Binary4RegisterShiftedOp # SBC(register-shifted) A1 A8-3
06 | 88 | " 10000 - =DataProc(v6T2) # MOV (immediate) 16-bit version |
| 89 0111x - =Binary4RegisterShiftedOp # RSC(register-shifted) A1 A8-2
94 | 89 | " 10100 - =DataProc(v6T2) # MOVT |
| 90 10001 - =Binary3RegisterShiftedTest # TST(register-shifted) A1 A8-4
58 | 90 | " 10x10 - ->msr_and_hints |
| 91 10011 - =Binary3RegisterShiftedTest # TEQ(register-shifted) A1 A8-4
52 | 91 +-- |
| 92 10101 - =Binary3RegisterShiftedTest # CMP(register-shifted) A1 A8-8
4 | 92 |
| 93 10111 - =Binary3RegisterShiftedTest # CMN(register-shifted) A1 A8-7
8 | 93 +-- dp_reg (See Section A5.2.1) |
| 94 1100x - =Binary4RegisterShiftedOp # ORR(register-shifted) A1 A8-2
32 | 94 | op1(24:20) op2(11:7) op3(6:5) |
| 95 1101x 00 =DataProc # LSL(register) A8-180 | 95 | 0000x - - =DataProc # AND(register) A8-36 |
| 96 " 01 =DataProc # LSR(register) A8-184 | 96 | 0001x - - =DataProc # EOR(register) A8-96 |
| 97 " 10 =DataProc # ASR(register) A8-42 | 97 | 0010x - - =DataProc # SUB(register) A8-422 |
| 98 " 11 =DataProc # ROR(register) A8-280 | 98 | 0011x - - =DataProc # RSB(register) A8-286 |
| 99 1110x - =Binary4RegisterShiftedOp # BIC(register-shifted) A1 A8-5
4 | 99 | 0100x - - =DataProc # ADD(register) A8-24 |
| 100 1111x - =Unary3RegisterShiftedOp # MVN(register-shifted) A1 A8-2
18 | 100 | 0101x - - =DataProc # ADC(register) A8-16 |
| 101 | 101 | 0110x - - =DataProc # SBC(register) A8-304 |
| 102 -- dp_immed (See Section A5.2.3) | 102 | 0111x - - =DataProc # RSC(register) A8-292 |
| 103 | 10001 - - =Test # TST(register) A8-456 |
| 104 | 10011 - - =Test # TEQ(register) A8-450 |
| 105 | 10101 - - =Test # CMP(register) A8-82 |
| 106 | 10111 - - =Test # CMN(register) A8-76 |
| 107 | 1100x - - =DataProc # ORR(register) A8-230 |
| 108 | 1101x 00000 00 =DataProc # MOV(register) A8-196 |
| 109 | " ~00000 00 =DataProc # LSL(immediate) A8-178 |
| 110 | " - 01 =DataProc # LSR(immediate) A8-182 |
| 111 | " - 10 =DataProc # ASR(immediate) A8-40 |
| 112 | " 00000 11 =DataProc # RRX A8-282 |
| 113 | " ~00000 11 =DataProc # ROR(immediate) A8-278 |
| 114 | 1110x - - =DataProc # BIC(register) A8-52 |
| 115 | 1111x - - =DataProc # MVN(register) A8-216 |
| 116 +-- |
| 117 |
| 118 +-- dp_reg_shifted (See Section A5.2.2) |
| 119 | op1(24:20) op2(6:5) |
| 120 | 0000x - =Binary4RegisterShiftedOp # AND(register-shifted) A1 A8
-38 |
| 121 | 0001x - =Binary4RegisterShiftedOp # EOR(register-shifted) A1 A8
-98 |
| 122 | 0010x - =Binary4RegisterShiftedOp # SUB(register-shifted) A1 A8
-424 |
| 123 | 0011x - =Binary4RegisterShiftedOp # RSB(register-shifted) A1 A8
-288 |
| 124 | 0100x - = Binary4RegisterShiftedOp Add_Rule_7_A1_P26 |
| 125 cccc0000100snnnnddddssss0tt1mmmm RegsNotPc |
| 126 | 0101x - =Binary4RegisterShiftedOp # ADC(register-shifted) A1 A8
-18 |
| 127 | 0110x - =Binary4RegisterShiftedOp # SBC(register-shifted) A1 A8
-306 |
| 128 | 0111x - =Binary4RegisterShiftedOp # RSC(register-shifted) A1 A8
-294 |
| 129 | 10001 - =Binary3RegisterShiftedTest # TST(register-shifted) A1 A8
-458 |
| 130 | 10011 - =Binary3RegisterShiftedTest # TEQ(register-shifted) A1 A8
-452 |
| 131 | 10101 - =Binary3RegisterShiftedTest # CMP(register-shifted) A1 A8
-84 |
| 132 | 10111 - =Binary3RegisterShiftedTest # CMN(register-shifted) A1 A8
-78 |
| 133 | 1100x - =Binary4RegisterShiftedOp # ORR(register-shifted) A1 A8
-232 |
| 134 | 1101x 00 =DataProc # LSL(register) A8-180 |
| 135 | " 01 =DataProc # LSR(register) A8-184 |
| 136 | " 10 =DataProc # ASR(register) A8-42 |
| 137 | " 11 =DataProc # ROR(register) A8-280 |
| 138 | 1110x - =Binary4RegisterShiftedOp # BIC(register-shifted) A1 A8
-54 |
| 139 | 1111x - =Unary3RegisterShiftedOp # MVN(register-shifted) A1 A8
-218 |
| 140 +-- |
| 141 |
| 142 +-- dp_immed (See Section A5.2.3) |
| 103 # We model this separately so we can recognize our mask instructions. | 143 # We model this separately so we can recognize our mask instructions. |
| 104 # Side-effect-wise it's identical to dp_reg, above. | 144 # Side-effect-wise it's identical to dp_reg, above. |
| 105 op(24:20) Rn(19:16) | 145 | op(24:20) Rn(19:16) |
| 106 0000x - =DataProc # AND(immediate) | 146 | 0000x - =DataProc # AND(immediate) |
| 107 0001x - =DataProc # EOR(immediate) | 147 | 0001x - =DataProc # EOR(immediate) |
| 108 0010x ~1111 =DataProc # SUB(immediate) | 148 | 0010x ~1111 =DataProc # SUB(immediate) |
| 109 " 1111 =DataProc # ADR | 149 | " 1111 =DataProc # ADR |
| 110 0011x - =DataProc # RSB(immediate) | 150 | 0011x - =DataProc # RSB(immediate) |
| 111 0100x ~1111 =DataProc # ADD(immediate) | 151 | 0100x ~1111 =DataProc # ADD(immediate) |
| 112 " 1111 =DataProc # ADR | 152 | " 1111 =DataProc # ADR |
| 113 0101x - =DataProc # ADC(immediate) | 153 | 0101x - =DataProc # ADC(immediate) |
| 114 0110x - =DataProc # SBC(immediate) | 154 | 0110x - =DataProc # SBC(immediate) |
| 115 0111x - =DataProc # RSC(immediate) | 155 | 0111x - =DataProc # RSC(immediate) |
| 116 10001 - =TestImmediate # TST(immediate) | 156 | 10001 - =TestImmediate # TST(immediate) |
| 117 10011 - =Test # TEQ(immediate) | 157 | 10011 - =Test # TEQ(immediate) |
| 118 10101 - =Test # CMP(immediate) | 158 | 10101 - =Test # CMP(immediate) |
| 119 10111 - =Test # CMN(immediate) | 159 | 10111 - =Test # CMN(immediate) |
| 120 1100x - =DataProc # ORR(immediate) | 160 | 1100x - =DataProc # ORR(immediate) |
| 121 1101x - =DataProc # MOV(immediate) | 161 | 1101x - =DataProc # MOV(immediate) |
| 122 1110x - =ImmediateBic # BIC(immediate) | 162 | 1110x - =ImmediateBic # BIC(immediate) |
| 123 1111x - =DataProc # MVN(immediate) | 163 | 1111x - =DataProc # MVN(immediate) |
| 124 | 164 +-- |
| 125 -- mult (See Section A5.2.5) | 165 |
| 126 op(23:20) | 166 +-- mult (See Section A5.2.5) |
| 127 000x =Multiply # MUL | 167 | op(23:20) |
| 128 001x =Multiply # MLA | 168 | 000x =Multiply # MUL |
| 129 0100 =LongMultiply(v6) # UMAAL | 169 | 001x =Multiply # MLA |
| 130 0101 =Undefined | 170 | 0100 =LongMultiply(v6) # UMAAL |
| 131 0110 =Multiply(v6T2) # MLS | 171 | 0101 =Undefined |
| 132 0111 =Undefined | 172 | 0110 =Multiply(v6T2) # MLS |
| 133 100x =LongMultiply # UMULL | 173 | 0111 =Undefined |
| 134 101x =LongMultiply # UMLAL | 174 | 100x =LongMultiply # UMULL |
| 135 110x =LongMultiply # SMULL | 175 | 101x =LongMultiply # UMLAL |
| 136 111x =LongMultiply # SMLAL | 176 | 110x =LongMultiply # SMULL |
| 137 | 177 | 111x =LongMultiply # SMLAL |
| 138 -- sat_add_sub (See Section A5.2.6) | 178 +-- |
| 139 op(22:21) | 179 |
| 140 00 =SatAddSub(v5TE) # QADD | 180 +-- sat_add_sub (See Section A5.2.6) |
| 141 01 =SatAddSub(v5TE) # QSUB | 181 | op(22:21) |
| 142 10 =SatAddSub(v5TE) # QDADD | 182 | 00 =SatAddSub(v5TE) # QADD |
| 143 11 =SatAddSub(v5TE) # QDSUB | 183 | 01 =SatAddSub(v5TE) # QSUB |
| 144 | 184 | 10 =SatAddSub(v5TE) # QDADD |
| 145 -- half_mult (See Section A5.2.7) | 185 | 11 =SatAddSub(v5TE) # QDSUB |
| 146 op1(22:21) op(5) | 186 +-- |
| 147 00 - =Multiply(v5TE) # SMLABB et al. | 187 |
| 148 01 0 =Multiply(v5TE) # SMLAWB et al. | 188 +-- half_mult (See Section A5.2.7) |
| 149 01 1 =Multiply(v5TE) # SMULWB et al. | 189 | op1(22:21) op(5) |
| 150 10 - =LongMultiply(v5TE) # SMLALBB | 190 | 00 - =Multiply(v5TE) # SMLABB et al. |
| 151 11 - =Multiply(v5TE) # SMULBB et al. | 191 | 01 0 =Multiply(v5TE) # SMLAWB et al. |
| 152 | 192 | 01 1 =Multiply(v5TE) # SMULWB et al. |
| 153 -- extra_load_store (See Section A5.2.8) | 193 | 10 - =LongMultiply(v5TE) # SMLALBB |
| 154 op2(6:5) op1(24:20) Rn(19:16) | 194 | 11 - =Multiply(v5TE) # SMULBB et al. |
| 155 01 xx0x0 - =StoreRegister # STRH(register) | 195 +-- |
| 156 " xx0x1 - =LoadRegister # LDRH(register) | 196 |
| 157 " xx1x0 - =StoreImmediate # STRH(immediate) | 197 +-- extra_load_store (See Section A5.2.8) |
| 158 " xx1x1 ~1111 =LoadImmediate # LDRH(immediate) | 198 | op2(6:5) op1(24:20) Rn(19:16) |
| 159 " " 1111 =LoadImmediate # LDRH(literal) | 199 | 01 xx0x0 - =StoreRegister # STRH(register) |
| 160 10 xx0x0 - =LoadDoubleR(v5TE) # LDRD(register) | 200 | " xx0x1 - =LoadRegister # LDRH(register) |
| 161 " xx0x1 - =LoadRegister # LDRSB(register) | 201 | " xx1x0 - =StoreImmediate # STRH(immediate) |
| 162 " xx1x0 ~1111 =LoadDoubleI(v5TE) # LDRD(immediate) | 202 | " xx1x1 ~1111 =LoadImmediate # LDRH(immediate) |
| 163 " " 1111 =LoadDoubleI(v5TE) # LDRD(literal) | 203 | " " 1111 =LoadImmediate # LDRH(literal) |
| 164 " xx1x1 ~1111 =LoadImmediate # LDRSB(immediate) | 204 | 10 xx0x0 - =LoadDoubleR(v5TE) # LDRD(register) |
| 165 " " 1111 =LoadImmediate # LDRSB(literal) | 205 | " xx0x1 - =LoadRegister # LDRSB(register) |
| 166 11 xx0x0 - =StoreRegister # STRD(register) | 206 | " xx1x0 ~1111 =LoadDoubleI(v5TE) # LDRD(immediate) |
| 167 " xx0x1 - =LoadRegister # LDRSH(register) | 207 | " " 1111 =LoadDoubleI(v5TE) # LDRD(literal) |
| 168 " xx1x0 - =StoreImmediate # STRD(immediate) | 208 | " xx1x1 ~1111 =LoadImmediate # LDRSB(immediate) |
| 169 " xx1x1 ~1111 =LoadImmediate # LDRSH(immediate) | 209 | " " 1111 =LoadImmediate # LDRSB(literal) |
| 170 " " 1111 =LoadImmediate # LDRSH(literal) | 210 | 11 xx0x0 - =StoreRegister # STRD(register) |
| 211 | " xx0x1 - =LoadRegister # LDRSH(register) |
| 212 | " xx1x0 - =StoreImmediate # STRD(immediate) |
| 213 | " xx1x1 ~1111 =LoadImmediate # LDRSH(immediate) |
| 214 | " " 1111 =LoadImmediate # LDRSH(literal) |
| 215 +-- |
| 171 | 216 |
| 172 # Unprivileged load-store table omitted: modeled as Forbidden. | 217 # Unprivileged load-store table omitted: modeled as Forbidden. |
| 173 # They are not expected in user code. | 218 # They are not expected in user code. |
| 174 | 219 |
| 175 -- sync (See Section A5.2.10) | 220 +-- sync (See Section A5.2.10) |
| 176 op(23:20) | 221 | op(23:20) |
| 177 0x00 =Deprecated # SWP, SWPB TODO(cbiffle): model these? | 222 | 0x00 =Deprecated # SWP, SWPB TODO(cbiffle): model these? |
| 178 1000 =StoreExclusive(v6) # STREX | 223 | 1000 =StoreExclusive(v6) # STREX |
| 179 1001 =LoadExclusive(v6) # LDREX | 224 | 1001 =LoadExclusive(v6) # LDREX |
| 180 1010 =StoreExclusive(v6K) # STREXD | 225 | 1010 =StoreExclusive(v6K) # STREXD |
| 181 1011 =LoadDoubleExclusive(v6K) # LDREXD | 226 | 1011 =LoadDoubleExclusive(v6K) # LDREXD |
| 182 1100 =StoreExclusive(v6K) # STREXB | 227 | 1100 =StoreExclusive(v6K) # STREXB |
| 183 1101 =LoadExclusive(v6K) # LDREXB | 228 | 1101 =LoadExclusive(v6K) # LDREXB |
| 184 1110 =StoreExclusive(v6K) # STREXH | 229 | 1110 =StoreExclusive(v6K) # STREXH |
| 185 1111 =LoadExclusive(v6K) # LDREXH | 230 | 1111 =LoadExclusive(v6K) # LDREXH |
| 186 - =Undefined(v6K) # Note on page A5-16 | 231 | - =Undefined(v6K) # Note on page A5-16 |
| 187 | 232 +-- |
| 188 -- msr_and_hints (See Section A5.2.11) | 233 |
| 189 op(22) op1(19:16) op2(7:0) | 234 +-- msr_and_hints (See Section A5.2.11) |
| 190 0 0000 0000_0000 =EffectiveNoOp(v6K,v6T2) # NOP | 235 | op(22) op1(19:16) op2(7:0) |
| 191 " " 0000_0001 =EffectiveNoOp(v6K) # YIELD | 236 | 0 0000 0000_0000 =EffectiveNoOp(v6K,v6T2) # NOP |
| 192 " " 0000_0010 =EffectiveNoOp(v6K) # WFE | 237 | " " 0000_0001 =EffectiveNoOp(v6K) # YIELD |
| 193 " " 0000_0011 =EffectiveNoOp(v6K) # WFI | 238 | " " 0000_0010 =EffectiveNoOp(v6K) # WFE |
| 194 " " 0000_0100 =EffectiveNoOp(v6K) # SEV | 239 | " " 0000_0011 =EffectiveNoOp(v6K) # WFI |
| 195 " " 1111_xxxx =EffectiveNoOp(v7) # DBG | 240 | " " 0000_0100 =EffectiveNoOp(v6K) # SEV |
| 196 " 0100 - =MoveToStatusRegister # MSR(immediate) | 241 | " " 1111_xxxx =EffectiveNoOp(v7) # DBG |
| 197 " 1x00 - =MoveToStatusRegister # MSR(immediate) | 242 | " 0100 - =MoveToStatusRegister # MSR(immediate) |
| 198 " xx01 - =Forbidden # MSR(immediate), ring0 version | 243 | " 1x00 - =MoveToStatusRegister # MSR(immediate) |
| 199 " xx1x - =Forbidden # MSR(immediate), ring0 version | 244 | " xx01 - =Forbidden # MSR(immediate), ring0 version |
| 200 1 - - =Forbidden # MSR(immediate), ring0 version | 245 | " xx1x - =Forbidden # MSR(immediate), ring0 version |
| 201 - - - =Forbidden # Unallocated hints, page A5-17 | 246 | 1 - - =Forbidden # MSR(immediate), ring0 version |
| 202 | 247 | - - - =Forbidden # Unallocated hints, page A5-17 |
| 203 -- misc (See Section A5.2.12) | 248 +-- |
| 204 op2(6:4) op(22:21) op1(19:16) | 249 |
| 205 000 x0 xxxx =DataProc # MRS | 250 +-- misc (See Section A5.2.12) |
| 206 " 01 xx00 =MoveToStatusRegister # MSR(register) | 251 | op2(6:4) op(22:21) op1(19:16) |
| 207 " 01 xx01 =Forbidden # MSR(register), ring0 version | 252 | 000 x0 xxxx =DataProc # MRS |
| 208 " " xx1x =Forbidden # MSR(register), ring0 version | 253 | " 01 xx00 =MoveToStatusRegister # MSR(register) |
| 209 " 11 - =Forbidden # MSR(register), ring0 version | 254 | " 01 xx01 =Forbidden # MSR(register), ring0 version |
| 210 001 01 - =BxBlx(v4T) # BX | 255 | " " xx1x =Forbidden # MSR(register), ring0 version |
| 211 " 11 - =DataProc(v6) # CLZ | 256 | " 11 - =Forbidden # MSR(register), ring0 version |
| 212 010 01 - =Forbidden # BXJ | 257 | 001 01 - =BxBlx(v4T) # BX |
| 213 011 01 - =BxBlx(v5T) # BLX(register) | 258 | " 11 - =DataProc(v6) # CLZ |
| 214 101 - - ->sat_add_sub | 259 | 010 01 - =Forbidden # BXJ |
| 215 111 01 - =Breakpoint(v5T) # BKPT | 260 | 011 01 - =BxBlx(v5T) # BLX(register) |
| 216 111 11 - =Forbidden # SMC | 261 | 101 - - ->sat_add_sub |
| 217 - - - =Undefined # Note on page A5-18 | 262 | 111 01 - =Breakpoint(v5T) # BKPT |
| 218 | 263 | 111 11 - =Forbidden # SMC |
| 219 -- load_store_word_byte (See Section A5.3) | 264 | - - - =Undefined # Note on page A5-18 |
| 265 +-- |
| 266 |
| 267 +-- load_store_word_byte (See Section A5.3) |
| 220 # The source table's "x not y" rules are implicit in the decoder, since we | 268 # The source table's "x not y" rules are implicit in the decoder, since we |
| 221 # evaluate patterns in order of specificity, not table order. | 269 # evaluate patterns in order of specificity, not table order. |
| 222 A(25) op1(24:20) B(4) Rn(19:16) | 270 | A(25) op1(24:20) B(4) Rn(19:16) |
| 223 0 xx0x0 - - =StoreImmediate # STR(immediate) | 271 | 0 xx0x0 - - =StoreImmediate # STR(immediate) |
| 224 1 xx0x0 0 - =StoreRegister # STR(register) | 272 | 1 xx0x0 0 - =StoreRegister # STR(register) |
| 225 0 0x010 - - =Forbidden # STRT | 273 | 0 0x010 - - =Forbidden # STRT |
| 226 1 0x010 0 - " | 274 | 1 0x010 0 - " |
| 227 0 xx0x1 - ~1111 =LoadImmediate # LDR(immediate) | 275 | 0 xx0x1 - ~1111 =LoadImmediate # LDR(immediate) |
| 228 " " " 1111 =LoadImmediate # LDR(literal) | 276 | " " " 1111 =LoadImmediate # LDR(literal) |
| 229 1 xx0x1 0 - =LoadRegister # LDR(register) | 277 | 1 xx0x1 0 - =LoadRegister # LDR(register) |
| 230 0 0x011 - - =Forbidden # LDRT | 278 | 0 0x011 - - =Forbidden # LDRT |
| 231 1 0x011 0 - " | 279 | 1 0x011 0 - " |
| 232 0 xx1x0 - - =StoreImmediate # STRB(immediate) | 280 | 0 xx1x0 - - =StoreImmediate # STRB(immediate) |
| 233 1 xx1x0 0 - =StoreRegister # STRB(register) | 281 | 1 xx1x0 0 - =StoreRegister # STRB(register) |
| 234 0 0x110 - - =Forbidden # STRBT | 282 | 0 0x110 - - =Forbidden # STRBT |
| 235 1 0x110 0 - " | 283 | 1 0x110 0 - " |
| 236 0 xx1x1 - ~1111 =LoadImmediate # LDRB(immediate) | 284 | 0 xx1x1 - ~1111 =LoadImmediate # LDRB(immediate) |
| 237 " " " 1111 =LoadImmediate # LDRB(literal) | 285 | " " " 1111 =LoadImmediate # LDRB(literal) |
| 238 1 xx1x1 0 - =LoadRegister # LDRB(register) | 286 | 1 xx1x1 0 - =LoadRegister # LDRB(register) |
| 239 0 0x111 - - =Forbidden # LDRBT | 287 | 0 0x111 - - =Forbidden # LDRBT |
| 240 1 0x111 0 - " | 288 | 1 0x111 0 - " |
| 241 | 289 +-- |
| 242 -- media (See Section A5.4) | 290 |
| 243 op1(24:20) op2(7:5) Rd(15:12) Rn(3:0) | 291 +-- media (See Section A5.4) |
| 244 000xx - - - ->parallel_add_sub # signed | 292 | op1(24:20) op2(7:5) Rd(15:12) Rn(3:0) |
| 245 001xx - - - ->parallel_add_sub # unsigned | 293 | 000xx - - - ->parallel_add_sub # signed |
| 246 01xxx - - - ->pack_sat_rev | 294 | 001xx - - - ->parallel_add_sub # unsigned |
| 247 10xxx - - - ->signed_mult | 295 | 01xxx - - - ->pack_sat_rev |
| 248 11000 000 1111 - =Multiply(v6) # USAD8 | 296 | 10xxx - - - ->signed_mult |
| 249 " 000 ~1111 - =Multiply(v6) # USADA8 | 297 | 11000 000 1111 - =Multiply(v6) # USAD8 |
| 250 1101x x10 - - =DataProc(v6T2) # SBFX | 298 | " 000 ~1111 - =Multiply(v6) # USADA8 |
| 251 1110x x00 - 1111 =DataProc(v6T2) # BFC | 299 | 1101x x10 - - =DataProc(v6T2) # SBFX |
| 252 " x00 - ~1111 =DataProc(v6T2) # BFI | 300 | 1110x x00 - 1111 =DataProc(v6T2) # BFC |
| 253 1111x x10 - - =DataProc(v6T2) # UBFX | 301 | " x00 - ~1111 =DataProc(v6T2) # BFI |
| 254 11111 111 - - =Roadblock # Permanently Undefined | 302 | 1111x x10 - - =DataProc(v6T2) # UBFX |
| 255 - - - - =Undefined # Note on page A5-21 | 303 | 11111 111 - - =Roadblock # Permanently Undefined |
| 256 | 304 | - - - - =Undefined # Note on page A5-21 |
| 257 -- parallel_add_sub (See Sections A5.4.1, A5.4.2) | 305 +-- |
| 306 |
| 307 +-- parallel_add_sub (See Sections A5.4.1, A5.4.2) |
| 258 # N.B. These instructions are defined as UNPREDICTABLE when using r15 as any | 308 # N.B. These instructions are defined as UNPREDICTABLE when using r15 as any |
| 259 # operand. This "UNPREDICTABLE" means the result is not defined, and is very | 309 # operand. This "UNPREDICTABLE" means the result is not defined, and is very |
| 260 # different than UNDEFINED. Since we don't allow these ops to write r15, and | 310 # different than UNDEFINED. Since we don't allow these ops to write r15, and |
| 261 # don't consider them suitable for producing a sandboxed address, we don't need | 311 # don't consider them suitable for producing a sandboxed address, we don't need |
| 262 # the result to be defined, and we don't model this here. | 312 # the result to be defined, and we don't model this here. |
| 263 op1(21:20) op2(7:5) | 313 | op1(21:20) op2(7:5) |
| 264 01 000 =DataProc(v6) # UADD16 | 314 | 01 000 =DataProc(v6) # UADD16 |
| 265 01 001 =DataProc(v6) # UASX | 315 | 01 001 =DataProc(v6) # UASX |
| 266 01 010 =DataProc(v6) # USAX | 316 | 01 010 =DataProc(v6) # USAX |
| 267 01 011 =DataProc(v6) # USUB16 | 317 | 01 011 =DataProc(v6) # USUB16 |
| 268 01 100 =DataProc(v6) # UADD8 | 318 | 01 100 =DataProc(v6) # UADD8 |
| 269 01 111 =DataProc(v6) # USUB8 | 319 | 01 111 =DataProc(v6) # USUB8 |
| 270 10 000 =DataProc(v6) # UQADD16 | 320 | 10 000 =DataProc(v6) # UQADD16 |
| 271 10 001 =DataProc(v6) # UQASX | 321 | 10 001 =DataProc(v6) # UQASX |
| 272 10 010 =DataProc(v6) # UQSAX | 322 | 10 010 =DataProc(v6) # UQSAX |
| 273 10 011 =DataProc(v6) # UQSUB16 | 323 | 10 011 =DataProc(v6) # UQSUB16 |
| 274 10 100 =DataProc(v6) # UQADD8 | 324 | 10 100 =DataProc(v6) # UQADD8 |
| 275 10 111 =DataProc(v6) # UQSUB8 | 325 | 10 111 =DataProc(v6) # UQSUB8 |
| 276 11 000 =DataProc(v6) # UHADD16 | 326 | 11 000 =DataProc(v6) # UHADD16 |
| 277 11 001 =DataProc(v6) # UHASX | 327 | 11 001 =DataProc(v6) # UHASX |
| 278 11 010 =DataProc(v6) # UHSAX | 328 | 11 010 =DataProc(v6) # UHSAX |
| 279 11 011 =DataProc(v6) # UHSUB16 | 329 | 11 011 =DataProc(v6) # UHSUB16 |
| 280 11 100 =DataProc(v6) # UHADD8 | 330 | 11 100 =DataProc(v6) # UHADD8 |
| 281 11 111 =DataProc(v6) # UHSUB8 | 331 | 11 111 =DataProc(v6) # UHSUB8 |
| 282 - - =Undefined # Note on page A5-23 | 332 | - - =Undefined # Note on page A5-23 |
| 283 | 333 +-- |
| 284 -- pack_sat_rev (See Section A5.4.3) | 334 |
| 285 op1(22:20) op2(7:5) A(19:16) | 335 +-- pack_sat_rev (See Section A5.4.3) |
| 286 000 xx0 - =PackSatRev(v6) # PKH | 336 | op1(22:20) op2(7:5) A(19:16) |
| 287 01x xx0 - =PackSatRev(v6) # SSAT | 337 | 000 xx0 - =PackSatRev(v6) # PKH |
| 288 11x xx0 - =PackSatRev(v6) # USAT | 338 | 01x xx0 - =PackSatRev(v6) # SSAT |
| 289 000 011 ~1111 =PackSatRev(v6) # SXTAB16 | 339 | 11x xx0 - =PackSatRev(v6) # USAT |
| 290 " " 1111 =PackSatRev(v6) # SXTB16 | 340 | 000 011 ~1111 =PackSatRev(v6) # SXTAB16 |
| 291 " 101 - =PackSatRev(v6) # SEL | 341 | " " 1111 =PackSatRev(v6) # SXTB16 |
| 292 010 001 - =PackSatRev(v6) # SSAT16 | 342 | " 101 - =PackSatRev(v6) # SEL |
| 293 " 011 ~1111 =PackSatRev(v6) # SXTAB | 343 | 010 001 - =PackSatRev(v6) # SSAT16 |
| 294 " " 1111 =PackSatRev(v6) # SXTB | 344 | " 011 ~1111 =PackSatRev(v6) # SXTAB |
| 295 011 001 - =PackSatRev(v6) # REV | 345 | " " 1111 =PackSatRev(v6) # SXTB |
| 296 " 011 ~1111 =PackSatRev(v6) # SXTAH | 346 | 011 001 - =PackSatRev(v6) # REV |
| 297 " " 1111 =PackSatRev(v6) # SXTH | 347 | " 011 ~1111 =PackSatRev(v6) # SXTAH |
| 298 011 101 - =PackSatRev(v6) # REV16 | 348 | " " 1111 =PackSatRev(v6) # SXTH |
| 299 100 011 ~1111 =PackSatRev(v6) # UXTAB16 | 349 | 011 101 - =PackSatRev(v6) # REV16 |
| 300 " " 1111 =PackSatRev(v6) # UXTB16 | 350 | 100 011 ~1111 =PackSatRev(v6) # UXTAB16 |
| 301 110 001 - =PackSatRev(v6) # USAT16 | 351 | " " 1111 =PackSatRev(v6) # UXTB16 |
| 302 " 011 ~1111 =PackSatRev(v6) # UXTAB | 352 | 110 001 - =PackSatRev(v6) # USAT16 |
| 303 " " 1111 =PackSatRev(v6) # UXTB | 353 | " 011 ~1111 =PackSatRev(v6) # UXTAB |
| 304 111 001 - =PackSatRev(v6T2) # RBIT | 354 | " " 1111 =PackSatRev(v6) # UXTB |
| 305 " 011 ~1111 =PackSatRev(v6) # UXTAH | 355 | 111 001 - =PackSatRev(v6T2) # RBIT |
| 306 " " 1111 =PackSatRev(v6) # UXTH | 356 | " 011 ~1111 =PackSatRev(v6) # UXTAH |
| 307 " 101 - =PackSatRev(v6) # REVSH | 357 | " " 1111 =PackSatRev(v6) # UXTH |
| 308 - - - =Undefined # Note on page A5-24 | 358 | " 101 - =PackSatRev(v6) # REVSH |
| 309 | 359 | - - - =Undefined # Note on page A5-24 |
| 310 -- signed_mult (See Section A5.4.4) | 360 +-- |
| 311 op1(22:20) op2(7:5) A(15:12) | 361 |
| 312 000 00x ~1111 =Multiply(v6T2) # SMLAD | 362 +-- signed_mult (See Section A5.4.4) |
| 313 " " 1111 =Multiply(v6T2) # SMUAD | 363 | op1(22:20) op2(7:5) A(15:12) |
| 314 " 01x ~1111 =Multiply(v6T2) # SMLSD | 364 | 000 00x ~1111 =Multiply(v6T2) # SMLAD |
| 315 " " - =Multiply(v6T2) # SMUSD | 365 | " " 1111 =Multiply(v6T2) # SMUAD |
| 316 100 00x - =LongMultiply(v6T2) # SMLALD | 366 | " 01x ~1111 =Multiply(v6T2) # SMLSD |
| 317 " 01x - =LongMultiply(v6T2) # SMLSLD | 367 | " " - =Multiply(v6T2) # SMUSD |
| 318 101 00x ~1111 =Multiply(v6T2) # SMMLA | 368 | 100 00x - =LongMultiply(v6T2) # SMLALD |
| 319 " " 1111 =Multiply(v6T2) # SMMUL | 369 | " 01x - =LongMultiply(v6T2) # SMLSLD |
| 320 " 11x - =Multiply(v6T2) # SMMLS | 370 | 101 00x ~1111 =Multiply(v6T2) # SMMLA |
| 321 - - - =Undefined # Note on page A5-26 | 371 | " " 1111 =Multiply(v6T2) # SMMUL |
| 322 | 372 | " 11x - =Multiply(v6T2) # SMMLS |
| 323 -- branch_block_xfer (See Section A5.5) | 373 | - - - =Undefined # Note on page A5-26 |
| 324 op(25:20) R(15) | 374 +-- |
| 325 0000x0 - =StoreImmediate # STMDA / STMED | 375 |
| 326 0000x1 - =LoadMultiple # LDMDA / LDMFA | 376 +-- branch_block_xfer (See Section A5.5) |
| 327 0010x0 - =StoreImmediate # STM / STMIA / STMEA | 377 | op(25:20) R(15) |
| 328 0010x1 - =LoadMultiple # LDM / LDMIA / LDMFD | 378 | 0000x0 - =StoreImmediate # STMDA / STMED |
| 329 0100x0 - =StoreImmediate # STMDB / STMFD | 379 | 0000x1 - =LoadMultiple # LDMDA / LDMFA |
| 330 0100x1 - =LoadMultiple # LDMDB / LDMEA | 380 | 0010x0 - =StoreImmediate # STM / STMIA / STMEA |
| 331 0110x0 - =StoreImmediate # STMIB / STMFA | 381 | 0010x1 - =LoadMultiple # LDM / LDMIA / LDMFD |
| 332 0110x1 - =LoadMultiple # LDMIB / LDMED | 382 | 0100x0 - =StoreImmediate # STMDB / STMFD |
| 333 0xx1x0 - =Forbidden # STM, ring0 version | 383 | 0100x1 - =LoadMultiple # LDMDB / LDMEA |
| 334 0xx1x1 0 =Forbidden # LDM, ring0 version | 384 | 0110x0 - =StoreImmediate # STMIB / STMFA |
| 335 " 1 =Forbidden # LDM, exception return | 385 | 0110x1 - =LoadMultiple # LDMIB / LDMED |
| 336 10xxxx - =Branch # B | 386 | 0xx1x0 - =Forbidden # STM, ring0 version |
| 337 11xxxx - =Branch # BL | 387 | 0xx1x1 0 =Forbidden # LDM, ring0 version |
| 338 | 388 | " 1 =Forbidden # LDM, exception return |
| 339 -- super_cop (See Section A5.6) | 389 | 10xxxx - =Branch # B |
| 390 | 11xxxx - =Branch # BL |
| 391 +-- |
| 392 |
| 393 +-- super_cop (See Section A5.6) |
| 340 # N.B. The ISA spec models the "Advanced SIMD" operations separately from other | 394 # N.B. The ISA spec models the "Advanced SIMD" operations separately from other |
| 341 # coprocessor operations. We don't, so the coproc column is omitted. | 395 # coprocessor operations. We don't, so the coproc column is omitted. |
| 342 op1(25:20) op(4) Rn(19:16) | 396 | op1(25:20) op(4) Rn(19:16) |
| 343 0xxxx0 - - =StoreCoprocessor # STC | 397 | 0xxxx0 - - =StoreCoprocessor # STC |
| 344 0xxxx1 - ~1111 =LoadCoprocessor # LDC(immediate), LDC2(immediate) | 398 | 0xxxx1 - ~1111 =LoadCoprocessor # LDC(immediate), LDC2(immediate
) |
| 345 " " 1111 =LoadCoprocessor # LDC(literal), LDC2(literal) | 399 | " " 1111 =LoadCoprocessor # LDC(literal), LDC2(literal) |
| 346 00000x - - =Undefined | 400 | 00000x - - =Undefined |
| 347 000100 - - =CoprocessorOp(v5TE) # MCRR, MCRR2 | 401 | 000100 - - =CoprocessorOp(v5TE) # MCRR, MCRR2 |
| 348 000101 - - =MoveDoubleFromCoprocessor(v5TE) # MRRC, MRRC2 | 402 | 000101 - - =MoveDoubleFromCoprocessor(v5TE) # MRRC, MRRC2 |
| 349 10xxxx 0 - =CoprocessorOp # CDP, CDP2 | 403 | 10xxxx 0 - =CoprocessorOp # CDP, CDP2 |
| 350 10xxx0 1 - =CoprocessorOp # MCR, MCR2 | 404 | 10xxx0 1 - =CoprocessorOp # MCR, MCR2 |
| 351 10xxx1 1 - =MoveFromCoprocessor # MRC, MRC2 | 405 | 10xxx1 1 - =MoveFromCoprocessor # MRC, MRC2 |
| 352 11xxxx - - =Forbidden # SVC (nee SWI) | 406 | 11xxxx - - =Forbidden # SVC (nee SWI) |
| 353 | 407 +-- |
| 354 -- unconditional (See Section A5.7) | 408 |
| 355 op1(27:20) op(4) Rn(19:16) | 409 +-- unconditional (See Section A5.7) |
| 356 0xxx_xxxx - - ->misc_hints_simd | 410 | op1(27:20) op(4) Rn(19:16) |
| 357 100x_x1x0 - - =Forbidden # SRS | 411 | 0xxx_xxxx - - ->misc_hints_simd |
| 358 100x_x0x1 - - =Forbidden # RFE | 412 | 100x_x1x0 - - =Forbidden # SRS |
| 359 101x_xxxx - - =Forbidden # BLX(immediate) | 413 | 100x_x0x1 - - =Forbidden # RFE |
| 360 1100_0x11 - ~1111 =LoadCoprocessor(v5) # LDC(immed), LDC2(immed) | 414 | 101x_xxxx - - =Forbidden # BLX(immediate) |
| 361 1100_1xx1 - 1111 =LoadCoprocessor(v5) # LDC(literal), LDC2(literal) | 415 | 1100_0x11 - ~1111 =LoadCoprocessor(v5) # LDC(immed), LDC2(immed) |
| 362 1101_xxx1 - 1111 =LoadCoprocessor(v5) # LDC(literal), LDC2(literal) | 416 | 1100_1xx1 - 1111 =LoadCoprocessor(v5) # LDC(literal), LDC2(literal
) |
| 363 1100_0x10 - - =StoreCoprocessor(v5) # STC, STC2 | 417 | 1101_xxx1 - 1111 =LoadCoprocessor(v5) # LDC(literal), LDC2(literal
) |
| 364 1100_1xx0 - - " | 418 | 1100_0x10 - - =StoreCoprocessor(v5) # STC, STC2 |
| 365 1101_xxx0 - - " | 419 | 1100_1xx0 - - " |
| 366 1100_0100 - - =CoprocessorOp(v6) # MCRR, MCRR2 | 420 | 1101_xxx0 - - " |
| 367 1100_0101 - - =MoveDoubleFromCoprocessor(v6) # MRRC, MRRC2 | 421 | 1100_0100 - - =CoprocessorOp(v6) # MCRR, MCRR2 |
| 368 1110_xxxx 0 - =CoprocessorOp(v5) # CDP, CDP2 | 422 | 1100_0101 - - =MoveDoubleFromCoprocessor(v6) # MRRC, MRRC2 |
| 369 1110_xxx0 1 - =CoprocessorOp(v5) # MCR, MCR2 | 423 | 1110_xxxx 0 - =CoprocessorOp(v5) # CDP, CDP2 |
| 370 1110_xxx1 1 - =MoveFromCoprocessor(v5) # MRC, MRC2 | 424 | 1110_xxx0 1 - =CoprocessorOp(v5) # MCR, MCR2 |
| 371 - - - =Undefined # Note on page A5-30 | 425 | 1110_xxx1 1 - =MoveFromCoprocessor(v5) # MRC, MRC2 |
| 372 | 426 | - - - =Undefined # Note on page A5-30 |
| 373 -- misc_hints_simd (See Section A5.7.1) | 427 +-- |
| 374 op1(26:20) op2(7:4) Rn(19:16) | 428 |
| 375 001_0000 xx0x xxx0 =Forbidden # CPS | 429 +-- misc_hints_simd (See Section A5.7.1) |
| 376 001_0000 0000 xxx1 =Forbidden # SETEND | 430 | op1(26:20) op2(7:4) Rn(19:16) |
| 377 01x_xxxx - - ->simd_dp | 431 | 001_0000 xx0x xxx0 =Forbidden # CPS |
| 378 100_xxx0 - - ->simd_load_store | 432 | 001_0000 0000 xxx1 =Forbidden # SETEND |
| 379 100_x001 - - =EffectiveNoOp(MP) # Unallocated memory hint | 433 | 01x_xxxx - - ->simd_dp |
| 380 100_x101 - - =EffectiveNoOp(v7) # PLI(immediate, literal) | 434 | 100_xxx0 - - ->simd_load_store |
| 381 101_x001 - ~1111 =EffectiveNoOp(MP) # PLDW(immediate) | 435 | 100_x001 - - =EffectiveNoOp(MP) # Unallocated memory hint |
| 382 " - 1111 =Unpredictable | 436 | 100_x101 - - =EffectiveNoOp(v7) # PLI(immediate, literal) |
| 383 101_x101 - ~1111 =EffectiveNoOp(v5TE) # PLD(immediate) | 437 | 101_x001 - ~1111 =EffectiveNoOp(MP) # PLDW(immediate) |
| 384 101_x101 - 1111 =EffectiveNoOp(v5TE) # PLD(literal) | 438 | " - 1111 =Unpredictable |
| 385 101_0111 0001 - =EffectiveNoOp(v6K) # CLREX | 439 | 101_x101 - ~1111 =EffectiveNoOp(v5TE) # PLD(immediate) |
| 386 " 0100 - =EffectiveNoOp(v6T2) # DSB | 440 | 101_x101 - 1111 =EffectiveNoOp(v5TE) # PLD(literal) |
| 387 " 0101 - =EffectiveNoOp(v7) # DMB | 441 | 101_0111 0001 - =EffectiveNoOp(v6K) # CLREX |
| 388 " 0110 - =EffectiveNoOp(v6T2) # ISB | 442 | " 0100 - =EffectiveNoOp(v6T2) # DSB |
| 389 10x_xx11 - - =Unpredictable | 443 | " 0101 - =EffectiveNoOp(v7) # DMB |
| 390 110_x001 xxx0 - =EffectiveNoOp(MP) # Unallocated memory hint | 444 | " 0110 - =EffectiveNoOp(v6T2) # ISB |
| 391 110_x101 xxx0 - =EffectiveNoOp(v7) # PLI(register) | 445 | 10x_xx11 - - =Unpredictable |
| 392 111_x001 xxx0 - =EffectiveNoOp(MP) # PLDW(register) | 446 | 110_x001 xxx0 - =EffectiveNoOp(MP) # Unallocated memory hint |
| 393 111_x101 xxx0 - =EffectiveNoOp(v5TE) # PLD(register) | 447 | 110_x101 xxx0 - =EffectiveNoOp(v7) # PLI(register) |
| 394 11x_xx11 xxx0 - =Unpredictable | 448 | 111_x001 xxx0 - =EffectiveNoOp(MP) # PLDW(register) |
| 395 - - - =Undefined # Note on page A5-31 | 449 | 111_x101 xxx0 - =EffectiveNoOp(v5TE) # PLD(register) |
| 396 | 450 | 11x_xx11 xxx0 - =Unpredictable |
| 397 -- simd_dp (See Section A7.4) | 451 | - - - =Undefined # Note on page A5-31 |
| 398 U(24) A(23:19) B(11:8) C(7:4) | 452 +-- |
| 399 - 0xxxx - - ->simd_dp_3same | 453 |
| 400 " 1x000 - 0xx1 ->simd_dp_1imm | 454 +-- simd_dp (See Section A7.4) |
| 401 " 1x001 - 0xx1 ->simd_dp_2shift | 455 | U(24) A(23:19) B(11:8) C(7:4) |
| 402 " 1x01x - 0xx1 " | 456 | - 0xxxx - - ->simd_dp_3same |
| 403 " 1x1xx - 0xx1 " | 457 | " 1x000 - 0xx1 ->simd_dp_1imm |
| 404 " 1xxxx - 1xx1 " | 458 | " 1x001 - 0xx1 ->simd_dp_2shift |
| 405 " 1x0xx - x0x0 ->simd_dp_3diff | 459 | " 1x01x - 0xx1 " |
| 406 " 1x10x - x0x0 " | 460 | " 1x1xx - 0xx1 " |
| 407 " 1x0xx - x1x0 ->simd_dp_2scalar | 461 | " 1xxxx - 1xx1 " |
| 408 " 1x10x - x1x0 " | 462 | " 1x0xx - x0x0 ->simd_dp_3diff |
| 409 0 1x11x - xxx0 =EffectiveNoOp # VEXT | 463 | " 1x10x - x0x0 " |
| 410 1 1x11x 0xxx xxx0 ->simd_dp_2misc | 464 | " 1x0xx - x1x0 ->simd_dp_2scalar |
| 411 " " 10xx xxx0 =EffectiveNoOp # VTBL, VTBX | 465 | " 1x10x - x1x0 " |
| 412 " " 1100 0xx0 =EffectiveNoOp # VDUP(scalar) | 466 | 0 1x11x - xxx0 =EffectiveNoOp # VEXT |
| 413 - - - - =Undefined # Note on page A7-10 | 467 | 1 1x11x 0xxx xxx0 ->simd_dp_2misc |
| 414 | 468 | " " 10xx xxx0 =EffectiveNoOp # VTBL, VTBX |
| 415 -- simd_dp_3same (See Section A7.4.1) | 469 | " " 1100 0xx0 =EffectiveNoOp # VDUP(scalar) |
| 470 | - - - - =Undefined # Note on page A7-10 |
| 471 +-- |
| 472 |
| 473 +-- simd_dp_3same (See Section A7.4.1) |
| 416 # This table is much larger than it needs to be, since we don't model these | 474 # This table is much larger than it needs to be, since we don't model these |
| 417 # ops (they work entirely in a separate register set, and cannot access memory). | 475 # ops (they work entirely in a separate register set, and cannot access memory). |
| 418 # Unfortunately there are some UNDEFINED holes here, so we have to be precise. | 476 # Unfortunately there are some UNDEFINED holes here, so we have to be precise. |
| 419 A(11:8) B(4) U(24) C(21:20) | 477 | A(11:8) B(4) U(24) C(21:20) |
| 420 0000 0 - - =EffectiveNoOp # VHADD | 478 | 0000 0 - - =EffectiveNoOp # VHADD |
| 421 " 1 - - =EffectiveNoOp # VQADD | 479 | " 1 - - =EffectiveNoOp # VQADD |
| 422 0001 0 - - =EffectiveNoOp # VRHADD | 480 | 0001 0 - - =EffectiveNoOp # VRHADD |
| 423 " 1 0 00 =EffectiveNoOp # VAND(register) | 481 | " 1 0 00 =EffectiveNoOp # VAND(register) |
| 424 " " " 01 =EffectiveNoOp # VBIC(register) | 482 | " " " 01 =EffectiveNoOp # VBIC(register) |
| 425 " " " 10 =EffectiveNoOp # VORR(register) | 483 | " " " 10 =EffectiveNoOp # VORR(register) |
| 426 " " " 11 =EffectiveNoOp # VORN(register) | 484 | " " " 11 =EffectiveNoOp # VORN(register) |
| 427 " 1 1 00 =EffectiveNoOp # VEOR(register) | 485 | " 1 1 00 =EffectiveNoOp # VEOR(register) |
| 428 " " " 01 =EffectiveNoOp # VBSL | 486 | " " " 01 =EffectiveNoOp # VBSL |
| 429 " " " 10 =EffectiveNoOp # VBIT | 487 | " " " 10 =EffectiveNoOp # VBIT |
| 430 " " " 11 =EffectiveNoOp # VBIF | 488 | " " " 11 =EffectiveNoOp # VBIF |
| 431 0010 0 - - =EffectiveNoOp # VHSUB | 489 | 0010 0 - - =EffectiveNoOp # VHSUB |
| 432 " 1 - - =EffectiveNoOp # VQSUB | 490 | " 1 - - =EffectiveNoOp # VQSUB |
| 433 0011 0 - - =EffectiveNoOp # VCGT(register) | 491 | 0011 0 - - =EffectiveNoOp # VCGT(register) |
| 434 " 1 - - =EffectiveNoOp # VCGE(register) | 492 | " 1 - - =EffectiveNoOp # VCGE(register) |
| 435 0100 0 - - =EffectiveNoOp # VSHL(register) | 493 | 0100 0 - - =EffectiveNoOp # VSHL(register) |
| 436 " 1 - - =EffectiveNoOp # VQSHL(register) | 494 | " 1 - - =EffectiveNoOp # VQSHL(register) |
| 437 0101 0 - - =EffectiveNoOp # VRSHL(register) | 495 | 0101 0 - - =EffectiveNoOp # VRSHL(register) |
| 438 " 1 - - =EffectiveNoOp # VQRSHL(register) | 496 | " 1 - - =EffectiveNoOp # VQRSHL(register) |
| 439 0110 - - - =EffectiveNoOp # VMAX, VMIN (integer) | 497 | 0110 - - - =EffectiveNoOp # VMAX, VMIN (integer) |
| 440 0111 0 - - =EffectiveNoOp # VABD, VABDL (integer) | 498 | 0111 0 - - =EffectiveNoOp # VABD, VABDL (integer) |
| 441 " 1 - - =EffectiveNoOp # VABA, VABAL | 499 | " 1 - - =EffectiveNoOp # VABA, VABAL |
| 442 1000 0 0 - =EffectiveNoOp # VADD(integer) | 500 | 1000 0 0 - =EffectiveNoOp # VADD(integer) |
| 443 " " 1 - =EffectiveNoOp # VSUB(integer) | 501 | " " 1 - =EffectiveNoOp # VSUB(integer) |
| 444 " 1 0 - =EffectiveNoOp # VTST(integer) | 502 | " 1 0 - =EffectiveNoOp # VTST(integer) |
| 445 " " 1 - =EffectiveNoOp # VCEQ(integer) | 503 | " " 1 - =EffectiveNoOp # VCEQ(integer) |
| 446 1001 0 - - =EffectiveNoOp # VMLA, VMLAL, VMLS, VMLSL (integer) | 504 | 1001 0 - - =EffectiveNoOp # VMLA, VMLAL, VMLS, VMLSL (intege
r) |
| 447 " 1 - - =EffectiveNoOp # VMUL, VMULL(integer/poly) | 505 | " 1 - - =EffectiveNoOp # VMUL, VMULL(integer/poly) |
| 448 1010 - - - =EffectiveNoOp # VPMAX, VPMIN(integer) | 506 | 1010 - - - =EffectiveNoOp # VPMAX, VPMIN(integer) |
| 449 1011 0 0 - =EffectiveNoOp # VQDMULH | 507 | 1011 0 0 - =EffectiveNoOp # VQDMULH |
| 450 " " 1 - =EffectiveNoOp # VQRDMULH | 508 | " " 1 - =EffectiveNoOp # VQRDMULH |
| 451 " 1 0 - =EffectiveNoOp # VPADD(integer) | 509 | " 1 0 - =EffectiveNoOp # VPADD(integer) |
| 452 1101 0 0 0x =EffectiveNoOp # VADD(float) | 510 | 1101 0 0 0x =EffectiveNoOp # VADD(float) |
| 453 " " " 1x =EffectiveNoOp # VSUB(float) | 511 | " " " 1x =EffectiveNoOp # VSUB(float) |
| 454 " " 1 0x =EffectiveNoOp # VPADD(float) | 512 | " " 1 0x =EffectiveNoOp # VPADD(float) |
| 455 " " " 1x =EffectiveNoOp # VABD(float) | 513 | " " " 1x =EffectiveNoOp # VABD(float) |
| 456 " 1 0 - =EffectiveNoOp # VMLA, VMLS(float) | 514 | " 1 0 - =EffectiveNoOp # VMLA, VMLS(float) |
| 457 " " 1 0x =EffectiveNoOp # VMUL(float) | 515 | " " 1 0x =EffectiveNoOp # VMUL(float) |
| 458 1110 0 0 0x =EffectiveNoOp # VCEQ(register) | 516 | 1110 0 0 0x =EffectiveNoOp # VCEQ(register) |
| 459 " " 1 0x =EffectiveNoOp # VCGE(register) | 517 | " " 1 0x =EffectiveNoOp # VCGE(register) |
| 460 " " " 1x =EffectiveNoOp # VCGT(register) | 518 | " " " 1x =EffectiveNoOp # VCGT(register) |
| 461 " 1 1 - =EffectiveNoOp # VACGE, VACGT, VACLE, VACLT | 519 | " 1 1 - =EffectiveNoOp # VACGE, VACGT, VACLE, VACLT |
| 462 1111 0 0 - =EffectiveNoOp # VMAX, VMIN(float) | 520 | 1111 0 0 - =EffectiveNoOp # VMAX, VMIN(float) |
| 463 " " 1 - =EffectiveNoOp # VPMAX, VPMIN(float) | 521 | " " 1 - =EffectiveNoOp # VPMAX, VPMIN(float) |
| 464 " 1 0 0x =EffectiveNoOp # VRECPS | 522 | " 1 0 0x =EffectiveNoOp # VRECPS |
| 465 " " 0 1x =EffectiveNoOp # VRSQRTS | 523 | " " 0 1x =EffectiveNoOp # VRSQRTS |
| 466 - - - - =Undefined # Note on page A7-12 | 524 | - - - - =Undefined # Note on page A7-12 |
| 467 | 525 +-- |
| 468 -- simd_dp_3diff (See Section A7.4.2) | 526 |
| 469 A(11:8) U(24) | 527 +-- simd_dp_3diff (See Section A7.4.2) |
| 470 000x - =EffectiveNoOp # VADDL | 528 | A(11:8) U(24) |
| 471 001x - =EffectiveNoOp # VSUBL | 529 | 000x - =EffectiveNoOp # VADDL |
| 472 0100 0 =EffectiveNoOp # VADDHN | 530 | 001x - =EffectiveNoOp # VSUBL |
| 473 " 1 =EffectiveNoOp # VRADDHN | 531 | 0100 0 =EffectiveNoOp # VADDHN |
| 474 0101 - =EffectiveNoOp # VABA, VABAL | 532 | " 1 =EffectiveNoOp # VRADDHN |
| 475 0110 0 =EffectiveNoOp # VSUBHN | 533 | 0101 - =EffectiveNoOp # VABA, VABAL |
| 476 " 1 =EffectiveNoOp # VRSUBHN | 534 | 0110 0 =EffectiveNoOp # VSUBHN |
| 477 0111 - =EffectiveNoOp # VABD, VABDL(integer) | 535 | " 1 =EffectiveNoOp # VRSUBHN |
| 478 10x0 - =EffectiveNoOp # VMLA, VMLAL, VMLS, VMLSL (integer) | 536 | 0111 - =EffectiveNoOp # VABD, VABDL(integer) |
| 479 10x1 0 =EffectiveNoOp # VQDMLAL, VQDMLSL | 537 | 10x0 - =EffectiveNoOp # VMLA, VMLAL, VMLS, VMLSL (integer) |
| 480 1100 - =EffectiveNoOp # VMUL, VMULL (integer) | 538 | 10x1 0 =EffectiveNoOp # VQDMLAL, VQDMLSL |
| 481 1101 0 =EffectiveNoOp # VQDMULL | 539 | 1100 - =EffectiveNoOp # VMUL, VMULL (integer) |
| 482 1110 - =EffectiveNoOp # VMUL, VMULL (polynomial) | 540 | 1101 0 =EffectiveNoOp # VQDMULL |
| 483 - - =Undefined # Note on page A7-15 | 541 | 1110 - =EffectiveNoOp # VMUL, VMULL (polynomial) |
| 484 | 542 | - - =Undefined # Note on page A7-15 |
| 485 -- simd_dp_2scalar (See Section A7.4.3) | 543 +-- |
| 486 A(11:8) U(24) | 544 |
| 487 0x0x - =EffectiveNoOp # VMLA, VMLS (scalar) | 545 +-- simd_dp_2scalar (See Section A7.4.3) |
| 488 0x10 - =EffectiveNoOp # VMLAL, VMLSL (scalar) | 546 | A(11:8) U(24) |
| 489 0x11 0 =EffectiveNoOp # VQDMLAL, VMQDLSL | 547 | 0x0x - =EffectiveNoOp # VMLA, VMLS (scalar) |
| 490 100x - =EffectiveNoOp # VMUL(scalar) | 548 | 0x10 - =EffectiveNoOp # VMLAL, VMLSL (scalar) |
| 491 1010 - =EffectiveNoOp # VMULL(scalar) | 549 | 0x11 0 =EffectiveNoOp # VQDMLAL, VMQDLSL |
| 492 1011 0 =EffectiveNoOp # VQDMULL | 550 | 100x - =EffectiveNoOp # VMUL(scalar) |
| 493 1100 - =EffectiveNoOp # VQDMULH | 551 | 1010 - =EffectiveNoOp # VMULL(scalar) |
| 494 1101 - =EffectiveNoOp # VQRDMULH | 552 | 1011 0 =EffectiveNoOp # VQDMULL |
| 495 - - =Undefined # Note on page A7-16 | 553 | 1100 - =EffectiveNoOp # VQDMULH |
| 496 | 554 | 1101 - =EffectiveNoOp # VQRDMULH |
| 497 -- simd_dp_2shift (See Section A7.4.4) | 555 | - - =Undefined # Note on page A7-16 |
| 498 A(11:8) U(24) B(6) L(7) | 556 +-- |
| 499 0000 - - - =EffectiveNoOp # VSHR | 557 |
| 500 0001 - - - =EffectiveNoOp # VSRA | 558 +-- simd_dp_2shift (See Section A7.4.4) |
| 501 0010 - - - =EffectiveNoOp # VRSHR | 559 | A(11:8) U(24) B(6) L(7) |
| 502 0011 - - - =EffectiveNoOp # VRSRA | 560 | 0000 - - - =EffectiveNoOp # VSHR |
| 503 0100 1 - - =EffectiveNoOp # VSRI | 561 | 0001 - - - =EffectiveNoOp # VSRA |
| 504 0101 0 - - =EffectiveNoOp # VSHL(immediate) | 562 | 0010 - - - =EffectiveNoOp # VRSHR |
| 505 0101 1 - - =EffectiveNoOp # VSLI | 563 | 0011 - - - =EffectiveNoOp # VRSRA |
| 506 011x - - - =EffectiveNoOp # VQSHL, VQSHLU(immediate) | 564 | 0100 1 - - =EffectiveNoOp # VSRI |
| 507 1000 0 0 0 =EffectiveNoOp # VSHRN | 565 | 0101 0 - - =EffectiveNoOp # VSHL(immediate) |
| 508 " " 1 - =EffectiveNoOp # VRSHRN | 566 | 0101 1 - - =EffectiveNoOp # VSLI |
| 509 " 1 0 - =EffectiveNoOp # VQSHRUN | 567 | 011x - - - =EffectiveNoOp # VQSHL, VQSHLU(immediate) |
| 510 " " 1 - =EffectiveNoOp # VQRSHRUN | 568 | 1000 0 0 0 =EffectiveNoOp # VSHRN |
| 511 1001 - 0 - =EffectiveNoOp # VQSHRN | 569 | " " 1 - =EffectiveNoOp # VRSHRN |
| 512 " - 1 - =EffectiveNoOp # VQRSHRN | 570 | " 1 0 - =EffectiveNoOp # VQSHRUN |
| 513 1010 - 0 - =EffectiveNoOp # VSHLL, VMOVL | 571 | " " 1 - =EffectiveNoOp # VQRSHRUN |
| 514 111x - - - =EffectiveNoOp # VCVT (floating- and fixed-point) | 572 | 1001 - 0 - =EffectiveNoOp # VQSHRN |
| 515 - - - - =Undefined # Note on page A7-17 | 573 | " - 1 - =EffectiveNoOp # VQRSHRN |
| 516 | 574 | 1010 - 0 - =EffectiveNoOp # VSHLL, VMOVL |
| 517 -- simd_dp_2misc (See Section A7.4.5) | 575 | 111x - - - =EffectiveNoOp # VCVT (floating- and fixed-point) |
| 518 A(17:16) B(10:6) | 576 | - - - - =Undefined # Note on page A7-17 |
| 519 00 0000x =EffectiveNoOp # VREV64 | 577 +-- |
| 520 " 0001x =EffectiveNoOp # VREV32 | 578 |
| 521 " 0010x =EffectiveNoOp # VREV16 | 579 +-- simd_dp_2misc (See Section A7.4.5) |
| 522 " 010xx =EffectiveNoOp # VPADDL | 580 | A(17:16) B(10:6) |
| 523 " 1000x =EffectiveNoOp # VCLS | 581 | 00 0000x =EffectiveNoOp # VREV64 |
| 524 " 1001x =EffectiveNoOp # VCLZ | 582 | " 0001x =EffectiveNoOp # VREV32 |
| 525 " 1010x =EffectiveNoOp # VCNT | 583 | " 0010x =EffectiveNoOp # VREV16 |
| 526 " 1011x =EffectiveNoOp # VMVN(register) | 584 | " 010xx =EffectiveNoOp # VPADDL |
| 527 " 110xx =EffectiveNoOp # VPADAL | 585 | " 1000x =EffectiveNoOp # VCLS |
| 528 " 1110x =EffectiveNoOp # VQABS | 586 | " 1001x =EffectiveNoOp # VCLZ |
| 529 " 1111x =EffectiveNoOp # VQNEG | 587 | " 1010x =EffectiveNoOp # VCNT |
| 530 01 x000x =EffectiveNoOp # VCGT (immediate #0) | 588 | " 1011x =EffectiveNoOp # VMVN(register) |
| 531 " x001x =EffectiveNoOp # VCGE (immediate #0) | 589 | " 110xx =EffectiveNoOp # VPADAL |
| 532 " x010x =EffectiveNoOp # VCEQ (immediate #0) | 590 | " 1110x =EffectiveNoOp # VQABS |
| 533 " x011x =EffectiveNoOp # VCLE (immediate #0) | 591 | " 1111x =EffectiveNoOp # VQNEG |
| 534 " x100x =EffectiveNoOp # VCLT (immediate #0) | 592 | 01 x000x =EffectiveNoOp # VCGT (immediate #0) |
| 535 " x110x =EffectiveNoOp # VABS | 593 | " x001x =EffectiveNoOp # VCGE (immediate #0) |
| 536 " x111x =EffectiveNoOp # VNEG | 594 | " x010x =EffectiveNoOp # VCEQ (immediate #0) |
| 537 10 0000x =EffectiveNoOp # VSWP | 595 | " x011x =EffectiveNoOp # VCLE (immediate #0) |
| 538 " 0001x =EffectiveNoOp # VTRN | 596 | " x100x =EffectiveNoOp # VCLT (immediate #0) |
| 539 " 0010x =EffectiveNoOp # VUZP | 597 | " x110x =EffectiveNoOp # VABS |
| 540 " 0011x =EffectiveNoOp # VZIP | 598 | " x111x =EffectiveNoOp # VNEG |
| 541 " 01000 =EffectiveNoOp # VMOVN | 599 | 10 0000x =EffectiveNoOp # VSWP |
| 542 " 01001 =EffectiveNoOp # VQMOVUN | 600 | " 0001x =EffectiveNoOp # VTRN |
| 543 " 0101x =EffectiveNoOp # VQMOVN | 601 | " 0010x =EffectiveNoOp # VUZP |
| 544 " 01100 =EffectiveNoOp # VSHLL | 602 | " 0011x =EffectiveNoOp # VZIP |
| 545 " 11x00 =EffectiveNoOp # VCVT (half- and single-precision) | 603 | " 01000 =EffectiveNoOp # VMOVN |
| 546 11 10x0x =EffectiveNoOp # VRECPE | 604 | " 01001 =EffectiveNoOp # VQMOVUN |
| 547 " 10x1x =EffectiveNoOp # VRSQRTE | 605 | " 0101x =EffectiveNoOp # VQMOVN |
| 548 " 11xxx =EffectiveNoOp # VCVT (float and integer) | 606 | " 01100 =EffectiveNoOp # VSHLL |
| 549 - - =Undefined # Note on page A7-19 | 607 | " 11x00 =EffectiveNoOp # VCVT (half- and single-precision) |
| 550 | 608 | 11 10x0x =EffectiveNoOp # VRECPE |
| 551 -- simd_dp_1imm (See Section A7.4.6) | 609 | " 10x1x =EffectiveNoOp # VRSQRTE |
| 552 op(5) cmode(11:8) | 610 | " 11xxx =EffectiveNoOp # VCVT (float and integer) |
| 553 0 0xx0 =EffectiveNoOp # VMOV(immediate) | 611 | - - =Undefined # Note on page A7-19 |
| 554 " 0xx1 =EffectiveNoOp # VORR(immediate) | 612 +-- |
| 555 " 10x0 =EffectiveNoOp # VMOV(immediate) | 613 |
| 556 " 10x1 =EffectiveNoOp # VORR(immediate) | 614 +-- simd_dp_1imm (See Section A7.4.6) |
| 557 " 11xx =EffectiveNoOp # VMOV(immediate) | 615 | op(5) cmode(11:8) |
| 558 1 0xx0 =EffectiveNoOp # VMVN(immediate) | 616 | 0 0xx0 =EffectiveNoOp # VMOV(immediate) |
| 559 " 0xx1 =EffectiveNoOp # VBIC(immediate) | 617 | " 0xx1 =EffectiveNoOp # VORR(immediate) |
| 560 " 10x0 =EffectiveNoOp # VMVN(immediate) | 618 | " 10x0 =EffectiveNoOp # VMOV(immediate) |
| 561 " 10x1 =EffectiveNoOp # VBIC(immediate) | 619 | " 10x1 =EffectiveNoOp # VORR(immediate) |
| 562 " 110x =EffectiveNoOp # VMVN(immediate) | 620 | " 11xx =EffectiveNoOp # VMOV(immediate) |
| 563 " 1110 =EffectiveNoOp # VMOV(immediate) | 621 | 1 0xx0 =EffectiveNoOp # VMVN(immediate) |
| 564 " 1111 =Undefined | 622 | " 0xx1 =EffectiveNoOp # VBIC(immediate) |
| 565 | 623 | " 10x0 =EffectiveNoOp # VMVN(immediate) |
| 566 -- simd_load_store (See Section A7.7) | 624 | " 10x1 =EffectiveNoOp # VBIC(immediate) |
| 625 | " 110x =EffectiveNoOp # VMVN(immediate) |
| 626 | " 1110 =EffectiveNoOp # VMOV(immediate) |
| 627 | " 1111 =Undefined |
| 628 +-- |
| 629 |
| 630 +-- simd_load_store (See Section A7.7) |
| 567 # This "table" is the first paragraph in A7.7. | 631 # This "table" is the first paragraph in A7.7. |
| 568 L(21) | 632 | L(21) |
| 569 0 ->simd_load_store_l0 | 633 | 0 ->simd_load_store_l0 |
| 570 1 ->simd_load_store_l1 | 634 | 1 ->simd_load_store_l1 |
| 571 | 635 +-- |
| 572 -- simd_load_store_l0 (See Section A7.7, Table A7-20) | 636 |
| 573 A(23) B(11:8) | 637 +-- simd_load_store_l0 (See Section A7.7, Table A7-20) |
| 574 0 0010 =VectorStore # VST1(multiple) | 638 | A(23) B(11:8) |
| 575 " 011x " | 639 | 0 0010 =VectorStore # VST1(multiple) |
| 576 " 1010 " | 640 | " 011x " |
| 577 " 0011 =VectorStore # VST2(multiple) | 641 | " 1010 " |
| 578 " 100x " | 642 | " 0011 =VectorStore # VST2(multiple) |
| 579 " 010x =VectorStore # VST3(multiple) | 643 | " 100x " |
| 580 " 000x =VectorStore # VST4(multiple) | 644 | " 010x =VectorStore # VST3(multiple) |
| 581 1 0x00 =VectorStore # VST1(single) | 645 | " 000x =VectorStore # VST4(multiple) |
| 582 " 1000 " | 646 | 1 0x00 =VectorStore # VST1(single) |
| 583 " 0x01 =VectorStore # VST2(single) | 647 | " 1000 " |
| 584 " 1001 " | 648 | " 0x01 =VectorStore # VST2(single) |
| 585 " 0x10 =VectorStore # VST3(single) | 649 | " 1001 " |
| 586 " 1010 " | 650 | " 0x10 =VectorStore # VST3(single) |
| 587 " 0x11 =VectorStore # VST4(single) | 651 | " 1010 " |
| 588 " 1011 " | 652 | " 0x11 =VectorStore # VST4(single) |
| 589 - - =Undefined # Note on page A7-27 | 653 | " 1011 " |
| 590 | 654 | - - =Undefined # Note on page A7-27 |
| 591 -- simd_load_store_l1 (See Section A7.7, Table A7-21) | 655 +-- |
| 592 A(23) B(11:8) | 656 |
| 593 0 0010 =VectorLoad # VLD1(multiple) | 657 +-- simd_load_store_l1 (See Section A7.7, Table A7-21) |
| 594 " 011x " | 658 | A(23) B(11:8) |
| 595 " 1010 " | 659 | 0 0010 =VectorLoad # VLD1(multiple) |
| 596 " 0011 =VectorLoad # VLD2(multiple) | 660 | " 011x " |
| 597 " 100x " | 661 | " 1010 " |
| 598 " 010x =VectorLoad # VLD3(multiple) | 662 | " 0011 =VectorLoad # VLD2(multiple) |
| 599 " 000x =VectorLoad # VLD4(multiple) | 663 | " 100x " |
| 600 1 0x00 =VectorLoad # VLD1(single) | 664 | " 010x =VectorLoad # VLD3(multiple) |
| 601 " 1000 " | 665 | " 000x =VectorLoad # VLD4(multiple) |
| 602 " 1100 =VectorLoad # VLD1(single, all lanes) | 666 | 1 0x00 =VectorLoad # VLD1(single) |
| 603 " 0x01 =VectorLoad # VLD2(single) | 667 | " 1000 " |
| 604 " 1001 " | 668 | " 1100 =VectorLoad # VLD1(single, all lanes) |
| 605 " 1101 =VectorLoad # VLD2(single, all lanes) | 669 | " 0x01 =VectorLoad # VLD2(single) |
| 606 " 0x10 =VectorLoad # VLD3(single) | 670 | " 1001 " |
| 607 " 1010 " | 671 | " 1101 =VectorLoad # VLD2(single, all lanes) |
| 608 " 1110 =VectorLoad # VLD3(single, all lanes) | 672 | " 0x10 =VectorLoad # VLD3(single) |
| 609 " 0x11 =VectorLoad # VLD4(single) | 673 | " 1010 " |
| 610 " 1011 " | 674 | " 1110 =VectorLoad # VLD3(single, all lanes) |
| 611 " 1111 =VectorLoad # VLD4(single, all lanes) | 675 | " 0x11 =VectorLoad # VLD4(single) |
| 612 - - =Undefined # Note on page A7-27 | 676 | " 1011 " |
| 677 | " 1111 =VectorLoad # VLD4(single, all lanes) |
| 678 | - - =Undefined # Note on page A7-27 |
| 679 +-- |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 9960043:
Finish separation of testing from sel_ldr validation. Also, automate (Closed)
Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/