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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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27 | 27 |
28 #include <assert.h> | 28 #include <assert.h> |
29 #include <stdio.h> | 29 #include <stdio.h> |
30 #include <stdarg.h> | 30 #include <stdarg.h> |
31 | 31 |
32 #include "v8.h" | 32 #include "v8.h" |
33 | 33 |
34 #if defined(V8_TARGET_ARCH_X64) | 34 #if defined(V8_TARGET_ARCH_X64) |
35 | 35 |
36 #include "disasm.h" | 36 #include "disasm.h" |
37 #include "lazy-instance.h" | |
38 | 37 |
39 namespace disasm { | 38 namespace disasm { |
40 | 39 |
41 enum OperandType { | 40 enum OperandType { |
42 UNSET_OP_ORDER = 0, | 41 UNSET_OP_ORDER = 0, |
43 // Operand size decides between 16, 32 and 64 bit operands. | 42 // Operand size decides between 16, 32 and 64 bit operands. |
44 REG_OPER_OP_ORDER = 1, // Register destination, operand source. | 43 REG_OPER_OP_ORDER = 1, // Register destination, operand source. |
45 OPER_REG_OP_ORDER = 2, // Operand destination, register source. | 44 OPER_REG_OP_ORDER = 2, // Operand destination, register source. |
46 // Fixed 8-bit operands. | 45 // Fixed 8-bit operands. |
47 BYTE_SIZE_OPERAND_FLAG = 4, | 46 BYTE_SIZE_OPERAND_FLAG = 4, |
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263 void InstructionTable::AddJumpConditionalShort() { | 262 void InstructionTable::AddJumpConditionalShort() { |
264 for (byte b = 0x70; b <= 0x7F; b++) { | 263 for (byte b = 0x70; b <= 0x7F; b++) { |
265 InstructionDesc* id = &instructions_[b]; | 264 InstructionDesc* id = &instructions_[b]; |
266 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered | 265 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered |
267 id->mnem = NULL; // Computed depending on condition code. | 266 id->mnem = NULL; // Computed depending on condition code. |
268 id->type = JUMP_CONDITIONAL_SHORT_INSTR; | 267 id->type = JUMP_CONDITIONAL_SHORT_INSTR; |
269 } | 268 } |
270 } | 269 } |
271 | 270 |
272 | 271 |
273 static v8::internal::LazyInstance<InstructionTable>::type instruction_table = | 272 static InstructionTable instruction_table; |
274 LAZY_INSTANCE_INITIALIZER; | |
275 | 273 |
276 | 274 |
277 static InstructionDesc cmov_instructions[16] = { | 275 static InstructionDesc cmov_instructions[16] = { |
278 {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 276 {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
279 {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 277 {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
280 {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 278 {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
281 {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 279 {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
282 {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 280 {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
283 {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 281 {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
284 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, | 282 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}, |
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1333 setRex(current); | 1331 setRex(current); |
1334 if (rex_w()) AppendToBuffer("REX.W "); | 1332 if (rex_w()) AppendToBuffer("REX.W "); |
1335 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3). | 1333 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3). |
1336 group_1_prefix_ = current; | 1334 group_1_prefix_ = current; |
1337 } else { // Not a prefix - an opcode. | 1335 } else { // Not a prefix - an opcode. |
1338 break; | 1336 break; |
1339 } | 1337 } |
1340 data++; | 1338 data++; |
1341 } | 1339 } |
1342 | 1340 |
1343 const InstructionDesc& idesc = instruction_table.Get().Get(current); | 1341 const InstructionDesc& idesc = instruction_table.Get(current); |
1344 byte_size_operand_ = idesc.byte_size_operation; | 1342 byte_size_operand_ = idesc.byte_size_operation; |
1345 switch (idesc.type) { | 1343 switch (idesc.type) { |
1346 case ZERO_OPERANDS_INSTR: | 1344 case ZERO_OPERANDS_INSTR: |
1347 if (current >= 0xA4 && current <= 0xA7) { | 1345 if (current >= 0xA4 && current <= 0xA7) { |
1348 // String move or compare operations. | 1346 // String move or compare operations. |
1349 if (group_1_prefix_ == REP_PREFIX) { | 1347 if (group_1_prefix_ == REP_PREFIX) { |
1350 // REP. | 1348 // REP. |
1351 AppendToBuffer("rep "); | 1349 AppendToBuffer("rep "); |
1352 } | 1350 } |
1353 if (rex_w()) AppendToBuffer("REX.W "); | 1351 if (rex_w()) AppendToBuffer("REX.W "); |
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1843 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { | 1841 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { |
1844 fprintf(f, " "); | 1842 fprintf(f, " "); |
1845 } | 1843 } |
1846 fprintf(f, " %s\n", buffer.start()); | 1844 fprintf(f, " %s\n", buffer.start()); |
1847 } | 1845 } |
1848 } | 1846 } |
1849 | 1847 |
1850 } // namespace disasm | 1848 } // namespace disasm |
1851 | 1849 |
1852 #endif // V8_TARGET_ARCH_X64 | 1850 #endif // V8_TARGET_ARCH_X64 |
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