Rollback of r11015, r11014, r11011, r11010 in trunk branch.

src/x64/disasm-x64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 16 matching lines @@
 
 #include <assert.h>
 #include <stdio.h>
 #include <stdarg.h>
 
 #include "v8.h"
 
 #if defined(V8_TARGET_ARCH_X64)
 
 #include "disasm.h"
-#include "lazy-instance.h"
 
 namespace disasm {
 
 enum OperandType {
   UNSET_OP_ORDER = 0,
   // Operand size decides between 16, 32 and 64 bit operands.
   REG_OPER_OP_ORDER = 1,  // Register destination, operand source.
   OPER_REG_OP_ORDER = 2,  // Operand destination, register source.
   // Fixed 8-bit operands.
   BYTE_SIZE_OPERAND_FLAG = 4,
@@ skipping 215 matching lines @@
 void InstructionTable::AddJumpConditionalShort() {
   for (byte b = 0x70; b <= 0x7F; b++) {
     InstructionDesc* id = &instructions_[b];
     ASSERT_EQ(NO_INSTR, id->type);  // Information not already entered
     id->mnem = NULL;  // Computed depending on condition code.
     id->type = JUMP_CONDITIONAL_SHORT_INSTR;
   }
 }
 
 
-static v8::internal::LazyInstance<InstructionTable>::type instruction_table =
-    LAZY_INSTANCE_INITIALIZER;
+static InstructionTable instruction_table;
 
 
 static InstructionDesc cmov_instructions[16] = {
   {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
@@ skipping 1048 matching lines @@
       setRex(current);
       if (rex_w()) AppendToBuffer("REX.W ");
     } else if ((current & 0xFE) == 0xF2) {  // Group 1 prefix (0xF2 or 0xF3).
       group_1_prefix_ = current;
     } else {  // Not a prefix - an opcode.
       break;
     }
     data++;
   }
 
-  const InstructionDesc& idesc = instruction_table.Get().Get(current);
+  const InstructionDesc& idesc = instruction_table.Get(current);
   byte_size_operand_ = idesc.byte_size_operation;
   switch (idesc.type) {
     case ZERO_OPERANDS_INSTR:
       if (current >= 0xA4 && current <= 0xA7) {
         // String move or compare operations.
         if (group_1_prefix_ == REP_PREFIX) {
           // REP.
           AppendToBuffer("rep ");
         }
         if (rex_w()) AppendToBuffer("REX.W ");
@@ skipping 489 matching lines @@
     for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
       fprintf(f, "  ");
     }
     fprintf(f, "  %s\n", buffer.start());
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_X64