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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
| 6 // met: | 6 // met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 843 } | 843 } |
| 844 | 844 |
| 845 // We have to use a temporary register for things that can be relocated even | 845 // We have to use a temporary register for things that can be relocated even |
| 846 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction | 846 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction |
| 847 // space. There is no guarantee that the relocated location can be similarly | 847 // space. There is no guarantee that the relocated location can be similarly |
| 848 // encoded. | 848 // encoded. |
| 849 bool Assembler::MustUseReg(RelocInfo::Mode rmode) { | 849 bool Assembler::MustUseReg(RelocInfo::Mode rmode) { |
| 850 return rmode != RelocInfo::NONE; | 850 return rmode != RelocInfo::NONE; |
| 851 } | 851 } |
| 852 | 852 |
| 853 | |
| 854 void Assembler::GenInstrRegister(Opcode opcode, | 853 void Assembler::GenInstrRegister(Opcode opcode, |
| 855 Register rs, | 854 Register rs, |
| 856 Register rt, | 855 Register rt, |
| 857 Register rd, | 856 Register rd, |
| 858 uint16_t sa, | 857 uint16_t sa, |
| 859 SecondaryField func) { | 858 SecondaryField func) { |
| 860 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); | 859 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); |
| 861 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) | 860 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
| 862 | (rd.code() << kRdShift) | (sa << kSaShift) | func; | 861 | (rd.code() << kRdShift) | (sa << kSaShift) | func; |
| 863 emit(instr); | 862 emit(instr); |
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| 2271 } | 2270 } |
| 2272 | 2271 |
| 2273 if (patched) { | 2272 if (patched) { |
| 2274 CPU::FlushICache(pc+2, sizeof(Address)); | 2273 CPU::FlushICache(pc+2, sizeof(Address)); |
| 2275 } | 2274 } |
| 2276 } | 2275 } |
| 2277 | 2276 |
| 2278 } } // namespace v8::internal | 2277 } } // namespace v8::internal |
| 2279 | 2278 |
| 2280 #endif // V8_TARGET_ARCH_MIPS | 2279 #endif // V8_TARGET_ARCH_MIPS |
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