MIPS: Branch delay slot and other optimizations.

src/mips/simulator-mips.h

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 291 matching lines @@
   void EnableStop(uint32_t code);
   void DisableStop(uint32_t code);
   void IncreaseStopCounter(uint32_t code);
   void PrintStopInfo(uint32_t code);
 
 
   // Executes one instruction.
   void InstructionDecode(Instruction* instr);
   // Execute one instruction placed in a branch delay slot.
   void BranchDelayInstructionDecode(Instruction* instr) {
+    if (instr->InstructionBits() == nopInstr) {
+      // Short-cut generic nop instructions. They are always valid and they
+      // never change the simulator state.
+      set_register(pc, reinterpret_cast<int32_t>(instr) +
+                       Instruction::kInstrSize);
+      return;
+    }
+
     if (instr->IsForbiddenInBranchDelay()) {
       V8_Fatal(__FILE__, __LINE__,
                "Eror:Unexpected %i opcode in a branch delay slot.",
                instr->OpcodeValue());
     }
     InstructionDecode(instr);
   }
 
   // ICache.
   static void CheckICache(v8::internal::HashMap* i_cache, Instruction* instr);
@@ skipping 101 matching lines @@
 
   static inline void UnregisterCTryCatch() {
     Simulator::current(Isolate::Current())->PopAddress();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // !defined(USE_SIMULATOR)
 #endif  // V8_MIPS_SIMULATOR_MIPS_H_