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Side by Side Diff: src/mips/macro-assembler-mips.h

Issue 9692048: MIPS: Added support for Loongson architectures. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 8 years, 9 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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219 inline void Move(Register dst_low, Register dst_high, FPURegister src) { 219 inline void Move(Register dst_low, Register dst_high, FPURegister src) {
220 mfc1(dst_low, src); 220 mfc1(dst_low, src);
221 mfc1(dst_high, FPURegister::from_code(src.code() + 1)); 221 mfc1(dst_high, FPURegister::from_code(src.code() + 1));
222 } 222 }
223 223
224 inline void Move(FPURegister dst, Register src_low, Register src_high) { 224 inline void Move(FPURegister dst, Register src_low, Register src_high) {
225 mtc1(src_low, dst); 225 mtc1(src_low, dst);
226 mtc1(src_high, FPURegister::from_code(dst.code() + 1)); 226 mtc1(src_high, FPURegister::from_code(dst.code() + 1));
227 } 227 }
228 228
229 // Conditional move.
229 void Move(FPURegister dst, double imm); 230 void Move(FPURegister dst, double imm);
231 void Movz(Register rd, Register rs, Register rt);
232 void Movn(Register rd, Register rs, Register rt);
233 void Movt(Register rd, Register rs, uint16_t cc = 0);
234 void Movf(Register rd, Register rs, uint16_t cc = 0);
235
236 void Clz(Register rd, Register rs);
230 237
231 // Jump unconditionally to given label. 238 // Jump unconditionally to given label.
232 // We NEED a nop in the branch delay slot, as it used by v8, for example in 239 // We NEED a nop in the branch delay slot, as it used by v8, for example in
233 // CodeGenerator::ProcessDeferred(). 240 // CodeGenerator::ProcessDeferred().
234 // Currently the branch delay slot is filled by the MacroAssembler. 241 // Currently the branch delay slot is filled by the MacroAssembler.
235 // Use rather b(Label) for code generation. 242 // Use rather b(Label) for code generation.
236 void jmp(Label* L) { 243 void jmp(Label* L) {
237 Branch(L); 244 Branch(L);
238 } 245 }
239 246
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685 // FPU macros. These do not handle special cases like NaN or +- inf. 692 // FPU macros. These do not handle special cases like NaN or +- inf.
686 693
687 // Convert unsigned word to double. 694 // Convert unsigned word to double.
688 void Cvt_d_uw(FPURegister fd, FPURegister fs, FPURegister scratch); 695 void Cvt_d_uw(FPURegister fd, FPURegister fs, FPURegister scratch);
689 void Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch); 696 void Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch);
690 697
691 // Convert double to unsigned word. 698 // Convert double to unsigned word.
692 void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch); 699 void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch);
693 void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch); 700 void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch);
694 701
702 void Trunc_w_d(FPURegister fd, FPURegister fs);
703 void Round_w_d(FPURegister fd, FPURegister fs);
704 void Floor_w_d(FPURegister fd, FPURegister fs);
705 void Ceil_w_d(FPURegister fd, FPURegister fs);
695 // Wrapper function for the different cmp/branch types. 706 // Wrapper function for the different cmp/branch types.
696 void BranchF(Label* target, 707 void BranchF(Label* target,
697 Label* nan, 708 Label* nan,
698 Condition cc, 709 Condition cc,
699 FPURegister cmp1, 710 FPURegister cmp1,
700 FPURegister cmp2, 711 FPURegister cmp2,
701 BranchDelaySlot bd = PROTECT); 712 BranchDelaySlot bd = PROTECT);
702 713
703 // Alternate (inline) version for better readability with USE_DELAY_SLOT. 714 // Alternate (inline) version for better readability with USE_DELAY_SLOT.
704 inline void BranchF(BranchDelaySlot bd, 715 inline void BranchF(BranchDelaySlot bd,
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1474 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x) 1485 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
1475 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 1486 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1476 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 1487 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1477 #else 1488 #else
1478 #define ACCESS_MASM(masm) masm-> 1489 #define ACCESS_MASM(masm) masm->
1479 #endif 1490 #endif
1480 1491
1481 } } // namespace v8::internal 1492 } } // namespace v8::internal
1482 1493
1483 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 1494 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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