Issue 9565007: Fix a register assignment bug in typed array stores without SSE3 available.

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Issue 9565007: Fix a register assignment bug in typed array stores without SSE3 available. (Closed)

Created:
8 years, 9 months ago by fschneider

Modified:
8 years, 9 months ago

Reviewers:
danno

CC:
v8-dev

Base URL:
http://v8.googlecode.com/svn/branches/bleeding_edge/

Visibility:
Public.

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Description

Fix a register assignment bug in typed array stores without SSE3 available. The old code used a separate HToInt32 instruction which had a wrong register constraint for the input register which caused wrong result when the stored value is used after a typed array store. (UseRegister instead of UseTempRegister) when no SSE3 is available. This change fixes it by replacing HToInt32 with the corresponding HChange instruction which has correct register contraints. TEST=mjsunit/compiler/regress-toint32.js Committed: https://code.google.com/p/v8/source/detail?r=10891

	Unified diffs	Side-by-side diffs	Delta from patch set	Stats (+54 lines, -139 lines)			Patch
M	src/arm/lithium-arm.cc	View		1 chunk	+0 lines, -25 lines	0 comments	Download
M	src/hydrogen.cc	View	1 2 3	3 chunks	+9 lines, -6 lines	0 comments	Download
M	src/hydrogen-instructions.h	View		2 chunks	+0 lines, -29 lines	0 comments	Download
M	src/ia32/lithium-ia32.cc	View		1 chunk	+0 lines, -28 lines	0 comments	Download
M	src/mips/lithium-mips.cc	View		1 chunk	+0 lines, -25 lines	0 comments	Download
M	src/x64/lithium-x64.cc	View		1 chunk	+0 lines, -26 lines	0 comments	Download
A	test/mjsunit/compiler/regress-toint32.js	View	1	1 chunk	+45 lines, -0 lines	0 comments	Download

Messages

Total messages: 2 (0 generated)

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lgtm

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Issue 9565007: Fix a register assignment bug in typed array stores without SSE3 available. (Closed)

Description

Patch Set 1 #

Patch Set 2 : corrected copyright file header #

Patch Set 3 : Fixed debug assert #

Patch Set 4 : Fixed assert for real #

Messages