MIPS: Added support for Loongson architectures.

test/cctest/test-assembler-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 201 matching lines @@
   __ ori(v0, v0, 0x8a00);  // 0x00009a30
   __ xori(v0, v0, 0x83cc);  // 0x000019fc
   __ Branch(&error, ne, v0, Operand(0x000019fc));
   __ nop();
   __ lui(v1, 0x8123);  // 0x81230000
   __ Branch(&error, ne, v1, Operand(0x81230000));
   __ nop();
 
   // Bit twiddling instructions & conditional moves.
   // Uses t0-t7 as set above.
-  __ clz(v0, t0);       // 29
-  __ clz(v1, t1);       // 19
+  __ Clz(v0, t0);       // 29
+  __ Clz(v1, t1);       // 19
   __ addu(v0, v0, v1);  // 48
-  __ clz(v1, t2);       // 3
+  __ Clz(v1, t2);       // 3
   __ addu(v0, v0, v1);  // 51
-  __ clz(v1, t7);       // 0
+  __ Clz(v1, t7);       // 0
   __ addu(v0, v0, v1);  // 51
   __ Branch(&error, ne, v0, Operand(51));
-  __ movn(a0, t3, t0);  // Move a0<-t3 (t0 is NOT 0).
+  __ Movn(a0, t3, t0);  // Move a0<-t3 (t0 is NOT 0).
   __ Ins(a0, t1, 12, 8);  // 0x7ff34fff
   __ Branch(&error, ne, a0, Operand(0x7ff34fff));
-  __ movz(a0, t6, t7);    // a0 not updated (t7 is NOT 0).
+  __ Movz(a0, t6, t7);    // a0 not updated (t7 is NOT 0).
   __ Ext(a1, a0, 8, 12);  // 0x34f
   __ Branch(&error, ne, a1, Operand(0x34f));
-  __ movz(a0, t6, v1);    // a0<-t6, v0 is 0, from 8 instr back.
+  __ Movz(a0, t6, v1);    // a0<-t6, v0 is 0, from 8 instr back.
   __ Branch(&error, ne, a0, Operand(t6));
 
   // Everything was correctly executed. Load the expected result.
   __ li(v0, 0x31415926);
   __ b(&exit);
   __ nop();
 
   __ bind(&error);
   // Got an error. Return a wrong result.
   __ li(v0, 666);
@@ skipping 325 matching lines @@
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ c(UN, D, f4, f6);
     __ bc1f(&neither_is_nan);
     __ nop();
     __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
     __ Branch(&outa_here);
 
     __ bind(&neither_is_nan);
 
-    __ c(OLT, D, f6, f4, 2);
-    __ bc1t(&less_than, 2);
+    if (kArchVariant == kLoongson) {
+      __ c(OLT, D, f6, f4);
+      __ bc1t(&less_than);
+    } else {
+      __ c(OLT, D, f6, f4, 2);
+      __ bc1t(&less_than, 2);
+    }
     __ nop();
     __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
     __ Branch(&outa_here);
 
     __ bind(&less_than);
     __ Addu(t0, zero_reg, Operand(1));
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, result)) );  // Set true.
 
 
     // This test-case should have additional tests.
@@ skipping 173 matching lines @@
     int32_t long_hi;
     int32_t long_lo;
     int32_t b_long_hi;
     int32_t b_long_lo;
   } T;
   T t;
 
   Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
-  if (CpuFeatures::IsSupported(FPU) && mips32r2) {
+  if (CpuFeatures::IsSupported(FPU) && kArchVariant == kMips32r2) {
     CpuFeatures::Scope scope(FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
 
     // Save the raw bits of the double.
     __ mfc1(t0, f0);
     __ mfc1(t1, f1);
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant)));
     __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
@@ skipping 481 matching lines @@
   Label target;
   __ beq(v0, v1, &target);
   __ nop();
   __ bne(v0, v1, &target);
   __ nop();
   __ bind(&target);
   __ nop();
 }
 
 #undef __