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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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3573 return Runtime::kAbort; | 3573 return Runtime::kAbort; |
3574 } | 3574 } |
3575 } | 3575 } |
3576 | 3576 |
3577 | 3577 |
3578 void StackCheckStub::Generate(MacroAssembler* masm) { | 3578 void StackCheckStub::Generate(MacroAssembler* masm) { |
3579 __ TailCallRuntime(Runtime::kStackGuard, 0, 1); | 3579 __ TailCallRuntime(Runtime::kStackGuard, 0, 1); |
3580 } | 3580 } |
3581 | 3581 |
3582 | 3582 |
| 3583 void InterruptStub::Generate(MacroAssembler* masm) { |
| 3584 __ TailCallRuntime(Runtime::kInterrupt, 0, 1); |
| 3585 } |
| 3586 |
| 3587 |
3583 void MathPowStub::Generate(MacroAssembler* masm) { | 3588 void MathPowStub::Generate(MacroAssembler* masm) { |
3584 CpuFeatures::Scope fpu_scope(FPU); | 3589 CpuFeatures::Scope fpu_scope(FPU); |
3585 const Register base = a1; | 3590 const Register base = a1; |
3586 const Register exponent = a2; | 3591 const Register exponent = a2; |
3587 const Register heapnumbermap = t1; | 3592 const Register heapnumbermap = t1; |
3588 const Register heapnumber = v0; | 3593 const Register heapnumber = v0; |
3589 const DoubleRegister double_base = f2; | 3594 const DoubleRegister double_base = f2; |
3590 const DoubleRegister double_exponent = f4; | 3595 const DoubleRegister double_exponent = f4; |
3591 const DoubleRegister double_result = f0; | 3596 const DoubleRegister double_result = f0; |
3592 const DoubleRegister double_scratch = f6; | 3597 const DoubleRegister double_scratch = f6; |
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7639 __ Ret(USE_DELAY_SLOT); | 7644 __ Ret(USE_DELAY_SLOT); |
7640 __ mov(v0, a0); | 7645 __ mov(v0, a0); |
7641 } | 7646 } |
7642 | 7647 |
7643 | 7648 |
7644 #undef __ | 7649 #undef __ |
7645 | 7650 |
7646 } } // namespace v8::internal | 7651 } } // namespace v8::internal |
7647 | 7652 |
7648 #endif // V8_TARGET_ARCH_MIPS | 7653 #endif // V8_TARGET_ARCH_MIPS |
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