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Issue 9378006: Make sure that top bits are zero when storing untagged 32 bit values (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 8 years, 10 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1633 void Assembler::movsxlq(Register dst, const Operand& src) { 1633 void Assembler::movsxlq(Register dst, const Operand& src) {
1634 EnsureSpace ensure_space(this); 1634 EnsureSpace ensure_space(this);
1635 emit_rex_64(dst, src); 1635 emit_rex_64(dst, src);
1636 emit(0x63); 1636 emit(0x63);
1637 emit_operand(dst, src); 1637 emit_operand(dst, src);
1638 } 1638 }
1639 1639
1640 1640
1641 void Assembler::movzxbq(Register dst, const Operand& src) { 1641 void Assembler::movzxbq(Register dst, const Operand& src) {
1642 EnsureSpace ensure_space(this); 1642 EnsureSpace ensure_space(this);
1643 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1644 // there is no need to make this a 64 bit operation.
1643 emit_optional_rex_32(dst, src); 1645 emit_optional_rex_32(dst, src);
1644 emit(0x0F); 1646 emit(0x0F);
1645 emit(0xB6); 1647 emit(0xB6);
1646 emit_operand(dst, src); 1648 emit_operand(dst, src);
1647 } 1649 }
1648 1650
1649 1651
1650 void Assembler::movzxbl(Register dst, const Operand& src) { 1652 void Assembler::movzxbl(Register dst, const Operand& src) {
1651 EnsureSpace ensure_space(this); 1653 EnsureSpace ensure_space(this);
1652 emit_optional_rex_32(dst, src); 1654 emit_optional_rex_32(dst, src);
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3041 // specially coded on x64 means that it is a relative 32 bit address, as used 3043 // specially coded on x64 means that it is a relative 32 bit address, as used
3042 // by branch instructions. 3044 // by branch instructions.
3043 return (1 << rmode_) & kApplyMask; 3045 return (1 << rmode_) & kApplyMask;
3044 } 3046 }
3045 3047
3046 3048
3047 3049
3048 } } // namespace v8::internal 3050 } } // namespace v8::internal
3049 3051
3050 #endif // V8_TARGET_ARCH_X64 3052 #endif // V8_TARGET_ARCH_X64
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