Allow building OS X 10.7 binaries.

binaries/mac_10.7/lib/valgrind/power-altivec-valgrind-s2.xml

Index: binaries/mac_10.7/lib/valgrind/power-altivec-valgrind-s2.xml
===================================================================
--- binaries/mac_10.7/lib/valgrind/power-altivec-valgrind-s2.xml	(revision 0)
+++ binaries/mac_10.7/lib/valgrind/power-altivec-valgrind-s2.xml	(revision 0)
@@ -0,0 +1,57 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.altivec-valgrind-s2">
+  <vector id="v4f" type="ieee_single" count="4"/>
+  <vector id="v4i32" type="int32" count="4"/>
+  <vector id="v8i16" type="int16" count="8"/>
+  <vector id="v16i8" type="int8" count="16"/>
+  <union id="vec128">
+    <field name="uint128" type="uint128"/>
+    <field name="v4_float" type="v4f"/>
+    <field name="v4_int32" type="v4i32"/>
+    <field name="v8_int16" type="v8i16"/>
+    <field name="v16_int8" type="v16i8"/>
+  </union>
+
+  <reg name="vr0s2" bitsize="128" type="vec128"/>
+  <reg name="vr1s2" bitsize="128" type="vec128"/>
+  <reg name="vr2s2" bitsize="128" type="vec128"/>
+  <reg name="vr3s2" bitsize="128" type="vec128"/>
+  <reg name="vr4s2" bitsize="128" type="vec128"/>
+  <reg name="vr5s2" bitsize="128" type="vec128"/>
+  <reg name="vr6s2" bitsize="128" type="vec128"/>
+  <reg name="vr7s2" bitsize="128" type="vec128"/>
+  <reg name="vr8s2" bitsize="128" type="vec128"/>
+  <reg name="vr9s2" bitsize="128" type="vec128"/>
+  <reg name="vr10s2" bitsize="128" type="vec128"/>
+  <reg name="vr11s2" bitsize="128" type="vec128"/>
+  <reg name="vr12s2" bitsize="128" type="vec128"/>
+  <reg name="vr13s2" bitsize="128" type="vec128"/>
+  <reg name="vr14s2" bitsize="128" type="vec128"/>
+  <reg name="vr15s2" bitsize="128" type="vec128"/>
+  <reg name="vr16s2" bitsize="128" type="vec128"/>
+  <reg name="vr17s2" bitsize="128" type="vec128"/>
+  <reg name="vr18s2" bitsize="128" type="vec128"/>
+  <reg name="vr19s2" bitsize="128" type="vec128"/>
+  <reg name="vr20s2" bitsize="128" type="vec128"/>
+  <reg name="vr21s2" bitsize="128" type="vec128"/>
+  <reg name="vr22s2" bitsize="128" type="vec128"/>
+  <reg name="vr23s2" bitsize="128" type="vec128"/>
+  <reg name="vr24s2" bitsize="128" type="vec128"/>
+  <reg name="vr25s2" bitsize="128" type="vec128"/>
+  <reg name="vr26s2" bitsize="128" type="vec128"/>
+  <reg name="vr27s2" bitsize="128" type="vec128"/>
+  <reg name="vr28s2" bitsize="128" type="vec128"/>
+  <reg name="vr29s2" bitsize="128" type="vec128"/>
+  <reg name="vr30s2" bitsize="128" type="vec128"/>
+  <reg name="vr31s2" bitsize="128" type="vec128"/>
+
+  <reg name="vscrs2" bitsize="32" group="vector"/>
+  <reg name="vrsaves2" bitsize="32" group="vector"/>
+</feature>