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1 /* | |
2 * Copyright (c) 2011 The Native Client Authors. All rights reserved. | |
3 * Use of this source code is governed by a BSD-style license that can be | |
4 * found in the LICENSE file. | |
5 */ | |
6 | |
7 #include <assert.h> | |
8 #include <elf.h> | |
9 #include <inttypes.h> | |
10 #include <stddef.h> | |
11 #include <stdio.h> | |
12 #include <stdlib.h> | |
13 #include <string.h> | |
14 #include "decoder.h" | |
15 | |
16 #undef TRUE | |
17 #define TRUE 1 | |
18 | |
19 #undef FALSE | |
20 #define FALSE 0 | |
21 | |
22 #include "decoder-x86_64-instruction-consts.c" | |
23 | |
24 %%{ | |
25 machine x86_64_decoder; | |
26 alphtype unsigned char; | |
27 | |
28 include decode_x86_64 "decoder-x86_64-instruction.rl"; | |
29 | |
30 main := (one_instruction | |
31 >{ | |
32 begin = p; | |
33 disp_type = DISPNONE; | |
34 imm_operand = IMMNONE; | |
35 imm2_operand = IMMNONE; | |
36 rex_prefix = FALSE; | |
37 data16_prefix = FALSE; | |
38 lock_prefix = FALSE; | |
39 repnz_prefix = FALSE; | |
40 repz_prefix = FALSE; | |
41 branch_not_taken = FALSE; | |
42 branch_taken = FALSE; | |
43 vex_prefix2 = 0xe0; | |
44 vex_prefix3 = 0x00; | |
45 } | |
46 @{ | |
47 switch (disp_type) { | |
48 case DISPNONE: instruction.rm.offset = 0; break; | |
49 case DISP8: instruction.rm.offset = (uint64_t) *disp; break; | |
50 case DISP16: instruction.rm.offset = | |
51 (uint64_t) (disp[0] + 256U * disp[1]); | |
52 break; | |
53 case DISP32: instruction.rm.offset = (uint64_t) | |
54 (disp[0] + 256U * (disp[1] + 256U * (disp[2] + 256U * (disp[3])))); | |
55 break; | |
56 case DISP64: instruction.rm.offset = (uint64_t) | |
57 (*disp + 256ULL * (disp[1] + 256ULL * (disp[2] + 256ULL * (disp[3] + | |
58 256ULL * (disp[4] + 256ULL * (disp[5] + 256ULL * (disp[6] + 256ULL * | |
59 disp[7]))))))); | |
60 break; | |
61 } | |
62 switch (imm_operand) { | |
63 case IMMNONE: instruction.imm[0] = 0; break; | |
64 case IMM2: instruction.imm[0] = imm[0] & 0x03; break; | |
65 case IMM8: instruction.imm[0] = imm[0]; break; | |
66 case IMM16: instruction.imm[0] = (uint64_t) (*imm + 256U * (imm[1])); | |
67 break; | |
68 case IMM32: instruction.imm[0] = (uint64_t) | |
69 (imm[0] + 256U * (imm[1] + 256U * (imm[2] + 256U * (imm[3])))); | |
70 break; | |
71 case IMM64: instruction.imm[0] = (uint64_t) | |
72 (imm[0] + 256LL * (imm[1] + 256ULL * (imm[2] + 256ULL * (imm[3] + | |
73 256ULL * (imm[4] + 256ULL * (imm[5] + 256ULL * (imm[6] + 256ULL * | |
74 imm[7]))))))); | |
75 break; | |
76 } | |
77 switch (imm2_operand) { | |
78 case IMMNONE: instruction.imm[1] = 0; break; | |
79 case IMM2: instruction.imm[1] = imm2[0] & 0x03; break; | |
80 case IMM8: instruction.imm[1] = imm2[0]; break; | |
81 case IMM16: instruction.imm[1] = (uint64_t) | |
82 (imm2[0] + 256U * (imm2[1])); | |
83 break; | |
84 case IMM32: instruction.imm[1] = (uint64_t) | |
85 (imm2[0] + 256U * (imm2[1] + 256U * (imm2[2] + 256U * (imm2[3])))); | |
86 break; | |
87 case IMM64: instruction.imm[1] = (uint64_t) | |
88 (*imm2 + 256ULL * (imm2[1] + 256ULL * (imm2[2] + 256ULL * (imm2[3] + | |
89 256ULL * (imm2[4] + 256ULL * (imm2[5] + 256ULL * (imm2[6] + 256ULL * | |
90 imm2[7]))))))); | |
91 break; | |
92 } | |
93 process_instruction(begin, p+1, &instruction, userdata); | |
94 })* | |
95 $!{ process_error(p, userdata); | |
96 result = 1; | |
97 goto error_detected; | |
98 }; | |
99 | |
100 }%% | |
101 | |
102 %% write data; | |
103 | |
104 #define base instruction.rm.base | |
105 #define index instruction.rm.index | |
106 #define scale instruction.rm.scale | |
107 #define rex_prefix instruction.prefix.rex | |
108 #define data16_prefix instruction.prefix.data16 | |
109 #define lock_prefix instruction.prefix.lock | |
110 #define repz_prefix instruction.prefix.repz | |
111 #define repnz_prefix instruction.prefix.repnz | |
112 #define branch_not_taken instruction.prefix.branch_not_taken | |
113 #define branch_taken instruction.prefix.branch_taken | |
114 #define operand0_type instruction.operands[0].type | |
115 #define operand1_type instruction.operands[1].type | |
116 #define operand2_type instruction.operands[2].type | |
117 #define operand3_type instruction.operands[3].type | |
118 #define operand4_type instruction.operands[4].type | |
119 #define operand0 instruction.operands[0].name | |
120 #define operand1 instruction.operands[1].name | |
121 #define operand2 instruction.operands[2].name | |
122 #define operand3 instruction.operands[3].name | |
123 #define operand4 instruction.operands[4].name | |
124 #define operands_count instruction.operands_count | |
125 #define instruction_name instruction.name | |
126 | |
127 enum { | |
128 REX_B = 1, | |
129 REX_X = 2, | |
130 REX_R = 4, | |
131 REX_W = 8 | |
132 }; | |
133 | |
134 enum disp_mode { | |
135 DISPNONE, | |
136 DISP8, | |
137 DISP16, | |
138 DISP32, | |
139 DISP64, | |
140 }; | |
141 | |
142 enum imm_mode { | |
143 IMMNONE, | |
144 IMM2, | |
145 IMM8, | |
146 IMM16, | |
147 IMM32, | |
148 IMM64 | |
149 }; | |
150 | |
151 int DecodeChunkAMD64(const uint8_t *data, size_t size, | |
152 process_instruction_func process_instruction, | |
153 process_error_func process_error, void *userdata) { | |
154 const uint8_t *p = data; | |
155 const uint8_t *pe = data + size; | |
156 const uint8_t *eof = pe; | |
157 const uint8_t *disp = NULL; | |
158 const uint8_t *imm = NULL; | |
159 const uint8_t *imm2 = NULL; | |
160 const uint8_t *begin; | |
161 uint8_t vex_prefix2, vex_prefix3; | |
162 enum disp_mode disp_type; | |
163 enum imm_mode imm_operand; | |
164 enum imm_mode imm2_operand; | |
165 struct instruction instruction; | |
166 int result = 0; | |
167 | |
168 int cs; | |
169 | |
170 %% write init; | |
171 %% write exec; | |
172 | |
173 error_detected: | |
174 return result; | |
175 } | |
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