Index: src/mips/cpu-mips.cc |
diff --git a/src/mips/cpu-mips.cc b/src/mips/cpu-mips.cc |
index a1e062c803d67aa24a1999870009a42592d0f97a..0d48470020379f3ef7e4911bd18f9adb4a52abd6 100644 |
--- a/src/mips/cpu-mips.cc |
+++ b/src/mips/cpu-mips.cc |
@@ -64,15 +64,19 @@ void CPU::FlushICache(void* start, size_t size) { |
} |
#if !defined (USE_SIMULATOR) |
+#if defined(ANDROID) |
+ // Bionic cacheflush can typically run in userland, avoiding kernel call. |
+ char *end = reinterpret_cast<char *>(start) + size; |
+ cacheflush( |
+ reinterpret_cast<intptr_t>(start), reinterpret_cast<intptr_t>(end), 0); |
+#else // ANDROID |
int res; |
- |
- // See http://www.linux-mips.org/wiki/Cacheflush_Syscall. |
+ // See http://www.linux-mips.org/wiki/Cacheflush_Syscall . |
res = syscall(__NR_cacheflush, start, size, ICACHE); |
- |
if (res) { |
V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache"); |
} |
- |
+#endif // ANDROID |
#else // USE_SIMULATOR. |
// Not generating mips instructions for C-code. This means that we are |
// building a mips emulator based target. We should notify the simulator |