OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
(...skipping 12 matching lines...) Expand all Loading... |
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
30 | 30 |
31 // The original source code covered by the above license above has been | 31 // The original source code covered by the above license above has been |
32 // modified significantly by Google Inc. | 32 // modified significantly by Google Inc. |
33 // Copyright 2011 the V8 project authors. All rights reserved. | 33 // Copyright 2012 the V8 project authors. All rights reserved. |
34 | 34 |
35 | 35 |
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_ | 36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_ |
37 #define V8_MIPS_ASSEMBLER_MIPS_H_ | 37 #define V8_MIPS_ASSEMBLER_MIPS_H_ |
38 | 38 |
39 #include <stdio.h> | 39 #include <stdio.h> |
40 #include "assembler.h" | 40 #include "assembler.h" |
41 #include "constants-mips.h" | 41 #include "constants-mips.h" |
42 #include "serialize.h" | 42 #include "serialize.h" |
43 | 43 |
(...skipping 131 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
175 | 175 |
176 // A few double registers are reserved: one as a scratch register and one to | 176 // A few double registers are reserved: one as a scratch register and one to |
177 // hold 0.0. | 177 // hold 0.0. |
178 // f28: 0.0 | 178 // f28: 0.0 |
179 // f30: scratch register. | 179 // f30: scratch register. |
180 static const int kNumReservedRegisters = 2; | 180 static const int kNumReservedRegisters = 2; |
181 static const int kNumAllocatableRegisters = kNumRegisters / 2 - | 181 static const int kNumAllocatableRegisters = kNumRegisters / 2 - |
182 kNumReservedRegisters; | 182 kNumReservedRegisters; |
183 | 183 |
184 | 184 |
185 static int ToAllocationIndex(FPURegister reg) { | 185 inline static int ToAllocationIndex(FPURegister reg); |
186 ASSERT(reg.code() % 2 == 0); | |
187 ASSERT(reg.code() / 2 < kNumAllocatableRegisters); | |
188 ASSERT(reg.is_valid()); | |
189 return (reg.code() / 2); | |
190 } | |
191 | 186 |
192 static FPURegister FromAllocationIndex(int index) { | 187 static FPURegister FromAllocationIndex(int index) { |
193 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 188 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
194 return from_code(index * 2); | 189 return from_code(index * 2); |
195 } | 190 } |
196 | 191 |
197 static const char* AllocationIndexToString(int index) { | 192 static const char* AllocationIndexToString(int index) { |
198 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 193 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
199 const char* const names[] = { | 194 const char* const names[] = { |
200 "f0", | 195 "f0", |
(...skipping 94 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
295 const FPURegister f23 = { 23 }; | 290 const FPURegister f23 = { 23 }; |
296 const FPURegister f24 = { 24 }; | 291 const FPURegister f24 = { 24 }; |
297 const FPURegister f25 = { 25 }; | 292 const FPURegister f25 = { 25 }; |
298 const FPURegister f26 = { 26 }; | 293 const FPURegister f26 = { 26 }; |
299 const FPURegister f27 = { 27 }; | 294 const FPURegister f27 = { 27 }; |
300 const FPURegister f28 = { 28 }; | 295 const FPURegister f28 = { 28 }; |
301 const FPURegister f29 = { 29 }; | 296 const FPURegister f29 = { 29 }; |
302 const FPURegister f30 = { 30 }; | 297 const FPURegister f30 = { 30 }; |
303 const FPURegister f31 = { 31 }; | 298 const FPURegister f31 = { 31 }; |
304 | 299 |
| 300 // Register aliases. |
| 301 // cp is assumed to be a callee saved register. |
| 302 static const Register& kLithiumScratchReg = s3; // Scratch register. |
| 303 static const Register& kLithiumScratchReg2 = s4; // Scratch register. |
| 304 static const Register& kRootRegister = s6; // Roots array pointer. |
| 305 static const Register& cp = s7; // JavaScript context pointer. |
| 306 static const Register& fp = s8_fp; // Alias for fp. |
| 307 static const DoubleRegister& kLithiumScratchDouble = f30; |
305 static const FPURegister& kDoubleRegZero = f28; | 308 static const FPURegister& kDoubleRegZero = f28; |
306 | 309 |
307 // FPU (coprocessor 1) control registers. | 310 // FPU (coprocessor 1) control registers. |
308 // Currently only FCSR (#31) is implemented. | 311 // Currently only FCSR (#31) is implemented. |
309 struct FPUControlRegister { | 312 struct FPUControlRegister { |
310 bool is_valid() const { return code_ == kFCSRRegister; } | 313 bool is_valid() const { return code_ == kFCSRRegister; } |
311 bool is(FPUControlRegister creg) const { return code_ == creg.code_; } | 314 bool is(FPUControlRegister creg) const { return code_ == creg.code_; } |
312 int code() const { | 315 int code() const { |
313 ASSERT(is_valid()); | 316 ASSERT(is_valid()); |
314 return code_; | 317 return code_; |
(...skipping 939 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1254 class EnsureSpace BASE_EMBEDDED { | 1257 class EnsureSpace BASE_EMBEDDED { |
1255 public: | 1258 public: |
1256 explicit EnsureSpace(Assembler* assembler) { | 1259 explicit EnsureSpace(Assembler* assembler) { |
1257 assembler->CheckBuffer(); | 1260 assembler->CheckBuffer(); |
1258 } | 1261 } |
1259 }; | 1262 }; |
1260 | 1263 |
1261 } } // namespace v8::internal | 1264 } } // namespace v8::internal |
1262 | 1265 |
1263 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1266 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
OLD | NEW |