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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
| 6 // met: | 6 // met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | 30 |
| 31 // The original source code covered by the above license above has been | 31 // The original source code covered by the above license above has been |
| 32 // modified significantly by Google Inc. | 32 // modified significantly by Google Inc. |
| 33 // Copyright 2011 the V8 project authors. All rights reserved. | 33 // Copyright 2012 the V8 project authors. All rights reserved. |
| 34 | 34 |
| 35 | 35 |
| 36 #ifndef V8_MIPS_ASSEMBLER_MIPS_INL_H_ | 36 #ifndef V8_MIPS_ASSEMBLER_MIPS_INL_H_ |
| 37 #define V8_MIPS_ASSEMBLER_MIPS_INL_H_ | 37 #define V8_MIPS_ASSEMBLER_MIPS_INL_H_ |
| 38 | 38 |
| 39 #include "mips/assembler-mips.h" | 39 #include "mips/assembler-mips.h" |
| 40 #include "cpu.h" | 40 #include "cpu.h" |
| 41 #include "debug.h" | 41 #include "debug.h" |
| 42 | 42 |
| 43 | 43 |
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| 71 Operand::Operand(Register rm) { | 71 Operand::Operand(Register rm) { |
| 72 rm_ = rm; | 72 rm_ = rm; |
| 73 } | 73 } |
| 74 | 74 |
| 75 | 75 |
| 76 bool Operand::is_reg() const { | 76 bool Operand::is_reg() const { |
| 77 return rm_.is_valid(); | 77 return rm_.is_valid(); |
| 78 } | 78 } |
| 79 | 79 |
| 80 | 80 |
| 81 int FPURegister::ToAllocationIndex(FPURegister reg) { |
| 82 ASSERT(reg.code() % 2 == 0); |
| 83 ASSERT(reg.code() / 2 < kNumAllocatableRegisters); |
| 84 ASSERT(reg.is_valid()); |
| 85 ASSERT(!reg.is(kDoubleRegZero)); |
| 86 ASSERT(!reg.is(kLithiumScratchDouble)); |
| 87 return (reg.code() / 2); |
| 88 } |
| 89 |
| 90 |
| 81 // ----------------------------------------------------------------------------- | 91 // ----------------------------------------------------------------------------- |
| 82 // RelocInfo. | 92 // RelocInfo. |
| 83 | 93 |
| 84 void RelocInfo::apply(intptr_t delta) { | 94 void RelocInfo::apply(intptr_t delta) { |
| 85 if (IsCodeTarget(rmode_)) { | 95 if (IsCodeTarget(rmode_)) { |
| 86 uint32_t scope1 = (uint32_t) target_address() & ~kImm28Mask; | 96 uint32_t scope1 = (uint32_t) target_address() & ~kImm28Mask; |
| 87 uint32_t scope2 = reinterpret_cast<uint32_t>(pc_) & ~kImm28Mask; | 97 uint32_t scope2 = reinterpret_cast<uint32_t>(pc_) & ~kImm28Mask; |
| 88 | 98 |
| 89 if (scope1 != scope2) { | 99 if (scope1 != scope2) { |
| 90 Assembler::JumpLabelToJumpRegister(pc_); | 100 Assembler::JumpLabelToJumpRegister(pc_); |
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| 335 } | 345 } |
| 336 *reinterpret_cast<Instr*>(pc_) = x; | 346 *reinterpret_cast<Instr*>(pc_) = x; |
| 337 pc_ += kInstrSize; | 347 pc_ += kInstrSize; |
| 338 CheckTrampolinePoolQuick(); | 348 CheckTrampolinePoolQuick(); |
| 339 } | 349 } |
| 340 | 350 |
| 341 | 351 |
| 342 } } // namespace v8::internal | 352 } } // namespace v8::internal |
| 343 | 353 |
| 344 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ | 354 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ |
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