Improve ASLR for arm64

Improve ASLR for arm64

R=ulan@chromium.org

[ulan, 2014-05-21 07:20:03]

lgtm

[Rodolph Perfetta, 2014-05-21 08:00:08]

https://chromiumcodereview.appspot.com/296853005/diff/1/src/platform-posix.cc
File src/platform-posix.cc (right):

https://chromiumcodereview.appspot.com/296853005/diff/1/src/platform-posix.cc...
src/platform-posix.cc:209: // Currently available CPUs have 40 bits of virtual
addressing with 39 for
DBC: arm64 has 48-bit virtual addresses

[danno, 2014-05-21 09:40:45]

Thanks for the heads-up, Rodolph. So, should arm64 work exactly like x64? i.e.
use a 46 bit hint? Chris, where did you get the 48/38 bit constraint?

[Rodolph Perfetta, 2014-05-21 10:01:01]

On 2014/05/21 09:40:45, danno wrote:
> Thanks for the heads-up, Rodolph. So, should arm64 work exactly like x64? i.e.
> use a 46 bit hint? Chris, where did you get the 48/38 bit constraint?

I should have been more accurate. The architecture support 48 bits addresses,
but how many bits is available will depend on the kernel config: with 4k pages
and 3 level of page table then you "only" have 40 bits of addresses, which is
probably where the initial number comes from. The kernel can be configured to
have a wider range of addresses using more page table levels or using 64k pages.
I guess going for the lowest denominator is the right thing to do. Updating the
comment would be good though.