| Index: src/compiler/x64/instruction-selector-x64.cc
|
| diff --git a/src/compiler/x64/instruction-selector-x64.cc b/src/compiler/x64/instruction-selector-x64.cc
|
| index b9ca427da2424f91047354e4737d290f6c86f578..04eb8f494d0ff2547ea4c02554f5658e80f9a05a 100644
|
| --- a/src/compiler/x64/instruction-selector-x64.cc
|
| +++ b/src/compiler/x64/instruction-selector-x64.cc
|
| @@ -2339,6 +2339,48 @@ void InstructionSelector::VisitAtomicExchange(Node* node) {
|
| Emit(code, 1, outputs, input_count, inputs);
|
| }
|
|
|
| +void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
|
| + X64OperandGenerator g(this);
|
| + Node* base = node->InputAt(0);
|
| + Node* index = node->InputAt(1);
|
| + Node* old_value = node->InputAt(2);
|
| + Node* new_value = node->InputAt(3);
|
| +
|
| + MachineType type = AtomicCompareExchangeRepresentationOf(node->op());
|
| + ArchOpcode opcode = kArchNop;
|
| + if (type == MachineType::Int8()) {
|
| + opcode = kAtomicCompareExchangeInt8;
|
| + } else if (type == MachineType::Uint8()) {
|
| + opcode = kAtomicCompareExchangeUint8;
|
| + } else if (type == MachineType::Int16()) {
|
| + opcode = kAtomicCompareExchangeInt16;
|
| + } else if (type == MachineType::Uint16()) {
|
| + opcode = kAtomicCompareExchangeUint16;
|
| + } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
|
| + opcode = kAtomicCompareExchangeWord32;
|
| + } else {
|
| + UNREACHABLE();
|
| + return;
|
| + }
|
| + InstructionOperand outputs[1];
|
| + AddressingMode addressing_mode;
|
| + InstructionOperand inputs[4];
|
| + size_t input_count = 0;
|
| + inputs[input_count++] = g.UseFixed(old_value, rax);
|
| + inputs[input_count++] = g.UseUniqueRegister(new_value);
|
| + inputs[input_count++] = g.UseUniqueRegister(base);
|
| + if (g.CanBeImmediate(index)) {
|
| + inputs[input_count++] = g.UseImmediate(index);
|
| + addressing_mode = kMode_MRI;
|
| + } else {
|
| + inputs[input_count++] = g.UseUniqueRegister(index);
|
| + addressing_mode = kMode_MR1;
|
| + }
|
| + outputs[0] = g.DefineAsFixed(node, rax);
|
| + InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
|
| + Emit(code, 1, outputs, input_count, inputs);
|
| +}
|
| +
|
| #define SIMD_TYPES(V) V(Int32x4)
|
|
|
| #define SIMD_ZERO_OP_LIST(V) \
|
|
|