[Atomics] Make Atomics.exchange a builtin using TF

src/compiler/arm64/code-generator-arm64.cc

Index: src/compiler/arm64/code-generator-arm64.cc
diff --git a/src/compiler/arm64/code-generator-arm64.cc b/src/compiler/arm64/code-generator-arm64.cc
index e7d5f2e9203a3173a83f8a4cbe86bbfc791f02a3..84615d0c334a23ba6818e2637052a6bbd4ec8067 100644
--- a/src/compiler/arm64/code-generator-arm64.cc
+++ b/src/compiler/arm64/code-generator-arm64.cc
@@ -99,6 +99,8 @@ class Arm64OperandConverter final : public InstructionOperandConverter {
 
   Register OutputRegister32() { return ToRegister(instr_->Output()).W(); }
 
+  Register TempRegister32() { return ToRegister(instr_->TempAt(0)).W(); }
+
   Operand InputOperand2_32(size_t index) {
     switch (AddressingModeField::decode(instr_->opcode())) {
       case kMode_None:
@@ -527,6 +529,17 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
     __ Dmb(InnerShareable, BarrierAll);                               \
   } while (0)
 
+#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(load_instr, store_instr)      \
+  do {                                                                 \
+    Label exchange;                                                    \
+    __ bind(&exchange);                                                \
+    __ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
+    __ load_instr(i.OutputRegister32(), i.TempRegister(0));            \
+    __ store_instr(i.TempRegister32(), i.InputRegister32(2),           \
+                   i.TempRegister(0));                                 \

[jbramley, 2017/03/08 11:11:07]

Acquire/release instructions shouldn't be used to control access to resources
that are also controlled via traditional barriers (like in
ASSEMBLE_ATOMIC_STORE_INTEGER above). For a given shared resource, we need to
pick one approach and use it consistently.

Ideally, these should all use acquire/release semantics since we know that
they're always available for AArch64, and theoretically they are faster.
However, the existing ones use traditional load/store+barrier sequences and
rewriting them will be a lot of work. Perhaps for now,
ASSEMBLE_ATOMIC_EXCHANGE_INTEGER should also use a dmb-based implementation.

+    __ cbnz(i.TempRegister32(), &exchange);                            \
+  } while (0)
+
 #define ASSEMBLE_IEEE754_BINOP(name)                                          \
   do {                                                                        \
     FrameScope scope(masm(), StackFrame::MANUAL);                             \
@@ -1631,6 +1644,23 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
              MemOperand(i.InputRegister(0), i.InputRegister(1)));
       __ Dmb(InnerShareable, BarrierAll);
       break;
+    case kAtomicExchangeInt8:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrb, stlxrb);
+      __ Sxtb(i.OutputRegister(0), i.OutputRegister(0));
+      break;
+    case kAtomicExchangeUint8:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrb, stlxrb);
+      break;
+    case kAtomicExchangeInt16:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrh, stlxrh);
+      __ Sxth(i.OutputRegister(0), i.OutputRegister(0));
+      break;
+    case kAtomicExchangeUint16:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrh, stlxrh);
+      break;
+    case kAtomicExchangeWord32:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxr, stlxr);
+      break;
   }
   return kSuccess;
 }  // NOLINT(readability/fn_size)