Index: src/compiler/arm/instruction-selector-arm.cc |
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc |
index da99db1049ba0de336f9e4e1863fd53a51e9c21f..a2d83e6db21e03d776d5f54906561134884401ab 100644 |
--- a/src/compiler/arm/instruction-selector-arm.cc |
+++ b/src/compiler/arm/instruction-selector-arm.cc |
@@ -2181,6 +2181,42 @@ void InstructionSelector::VisitAtomicStore(Node* node) { |
Emit(code, 0, nullptr, input_count, inputs); |
} |
+void InstructionSelector::VisitAtomicExchange(Node* node) { |
+ ArmOperandGenerator g(this); |
+ Node* base = node->InputAt(0); |
+ Node* index = node->InputAt(1); |
+ Node* value = node->InputAt(2); |
+ ArchOpcode opcode = kArchNop; |
+ MachineType type = AtomicExchangeRepresentationOf(node->op()); |
+ if (type == MachineType::Int8()) { |
+ opcode = kAtomicExchangeInt8; |
+ } else if (type == MachineType::Uint8()) { |
+ opcode = kAtomicExchangeUint8; |
+ } else if (type == MachineType::Int16()) { |
+ opcode = kAtomicExchangeInt16; |
+ } else if (type == MachineType::Uint16()) { |
+ opcode = kAtomicExchangeUint16; |
+ } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { |
+ opcode = kAtomicExchangeWord32; |
+ } else { |
+ UNREACHABLE(); |
+ return; |
+ } |
+ |
+ AddressingMode addressing_mode = kMode_Offset_RR; |
+ InstructionOperand inputs[3]; |
+ size_t input_count = 0; |
+ inputs[input_count++] = g.UseUniqueRegister(base); |
+ inputs[input_count++] = g.UseUniqueRegister(index); |
+ inputs[input_count++] = g.UseUniqueRegister(value); |
+ InstructionOperand outputs[1]; |
+ outputs[0] = g.UseUniqueRegister(node); |
+ InstructionOperand temp[1]; |
+ temp[0] = g.TempRegister(); |
+ InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); |
+ Emit(code, 1, outputs, input_count, inputs, 1, temp); |
+} |
+ |
#define SIMD_TYPE_LIST(V) \ |
V(Float32x4) \ |
V(Int32x4) \ |