[Atomics] Make Atomics.exchange a builtin using TF

src/compiler/arm64/code-generator-arm64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm64/frames-arm64.h"
 #include "src/arm64/macro-assembler-arm64.h"
 #include "src/compilation-info.h"
 #include "src/compiler/code-generator-impl.h"
@@ skipping 81 matching lines @@
   Operand InputOperand64(size_t index) { return InputOperand(index); }
 
   Operand InputOperand32(size_t index) {
     return ToOperand32(instr_->InputAt(index));
   }
 
   Register OutputRegister64() { return OutputRegister(); }
 
   Register OutputRegister32() { return ToRegister(instr_->Output()).W(); }
 
+  Register TempRegister32() { return ToRegister(instr_->TempAt(0)).W(); }
+
   Operand InputOperand2_32(size_t index) {
     switch (AddressingModeField::decode(instr_->opcode())) {
       case kMode_None:
         return InputOperand32(index);
       case kMode_Operand2_R_LSL_I:
         return Operand(InputRegister32(index), LSL, InputInt5(index + 1));
       case kMode_Operand2_R_LSR_I:
         return Operand(InputRegister32(index), LSR, InputInt5(index + 1));
       case kMode_Operand2_R_ASR_I:
         return Operand(InputRegister32(index), ASR, InputInt5(index + 1));
@@ skipping 408 matching lines @@
   } while (0)
 
 #define ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr)                      \
   do {                                                                \
     __ Dmb(InnerShareable, BarrierAll);                               \
     __ asm_instr(i.InputRegister(2),                                  \
                  MemOperand(i.InputRegister(0), i.InputRegister(1))); \
     __ Dmb(InnerShareable, BarrierAll);                               \
   } while (0)
 
+#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(load_instr, store_instr)      \
+  do {                                                                 \
+    Label exchange;                                                    \
+    __ bind(&exchange);                                                \
+    __ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
+    __ load_instr(i.OutputRegister32(), i.TempRegister(0));            \
+    __ store_instr(i.TempRegister32(), i.InputRegister32(2),           \
+                   i.TempRegister(0));                                 \

[jbramley, 2017/03/08 11:11:07]

Acquire/release instructions shouldn't be used to control access to resources
that are also controlled via traditional barriers (like in
ASSEMBLE_ATOMIC_STORE_INTEGER above). For a given shared resource, we need to
pick one approach and use it consistently.

Ideally, these should all use acquire/release semantics since we know that
they're always available for AArch64, and theoretically they are faster.
However, the existing ones use traditional load/store+barrier sequences and
rewriting them will be a lot of work. Perhaps for now,
ASSEMBLE_ATOMIC_EXCHANGE_INTEGER should also use a dmb-based implementation.

+    __ cbnz(i.TempRegister32(), &exchange);                            \
+  } while (0)
+
 #define ASSEMBLE_IEEE754_BINOP(name)                                          \
   do {                                                                        \
     FrameScope scope(masm(), StackFrame::MANUAL);                             \
     __ CallCFunction(ExternalReference::ieee754_##name##_function(isolate()), \
                      0, 2);                                                   \
   } while (0)
 
 #define ASSEMBLE_IEEE754_UNOP(name)                                           \
   do {                                                                        \
     FrameScope scope(masm(), StackFrame::MANUAL);                             \
@@ skipping 1084 matching lines @@
       break;
     case kAtomicStoreWord16:
       ASSEMBLE_ATOMIC_STORE_INTEGER(Strh);
       break;
     case kAtomicStoreWord32:
       __ Dmb(InnerShareable, BarrierAll);
       __ Str(i.InputRegister32(2),
              MemOperand(i.InputRegister(0), i.InputRegister(1)));
       __ Dmb(InnerShareable, BarrierAll);
       break;
+    case kAtomicExchangeInt8:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrb, stlxrb);
+      __ Sxtb(i.OutputRegister(0), i.OutputRegister(0));
+      break;
+    case kAtomicExchangeUint8:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrb, stlxrb);
+      break;
+    case kAtomicExchangeInt16:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrh, stlxrh);
+      __ Sxth(i.OutputRegister(0), i.OutputRegister(0));
+      break;
+    case kAtomicExchangeUint16:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxrh, stlxrh);
+      break;
+    case kAtomicExchangeWord32:
+      ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxr, stlxr);
+      break;
   }
   return kSuccess;
 }  // NOLINT(readability/fn_size)
 
 
 // Assemble branches after this instruction.
 void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
   Arm64OperandConverter i(this, instr);
   Label* tlabel = branch->true_label;
   Label* flabel = branch->false_label;
@@ skipping 533 matching lines @@
       padding_size -= kInstructionSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8