Index: src/compiler/arm/instruction-selector-arm.cc |
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc |
index ceb5b2507f809d912dd4268a3937462274428786..a2f2d23f7c40aa9448ecd5381cf4723571138970 100644 |
--- a/src/compiler/arm/instruction-selector-arm.cc |
+++ b/src/compiler/arm/instruction-selector-arm.cc |
@@ -957,76 +957,83 @@ void InstructionSelector::VisitWord32Sar(Node* node) { |
void InstructionSelector::VisitInt32PairAdd(Node* node) { |
ArmOperandGenerator g(this); |
- // We use UseUniqueRegister here to avoid register sharing with the output |
- // registers. |
- InstructionOperand inputs[] = { |
- g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)), |
- g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))}; |
- |
- InstructionOperand outputs[] = { |
- g.DefineAsRegister(node), |
- g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
- |
- Emit(kArmAddPair, 2, outputs, 4, inputs); |
+ Node* projection1 = NodeProperties::FindProjection(node, 1); |
+ if (projection1) { |
+ // We use UseUniqueRegister here to avoid register sharing with the output |
+ // registers. |
+ InstructionOperand inputs[] = { |
+ g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)), |
+ g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))}; |
+ |
+ InstructionOperand outputs[] = { |
+ g.DefineAsRegister(node), |
+ g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
+ |
+ Emit(kArmAddPair, 2, outputs, 4, inputs); |
+ } else { |
+ // The high word of the result is not used, so we emit the standard 32 bit |
+ // instruction. |
+ Emit(kArmAdd | AddressingModeField::encode(kMode_Operand2_R), |
+ g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), |
+ g.UseRegister(node->InputAt(2))); |
+ } |
} |
void InstructionSelector::VisitInt32PairSub(Node* node) { |
ArmOperandGenerator g(this); |
- // We use UseUniqueRegister here to avoid register sharing with the output |
- // register. |
- InstructionOperand inputs[] = { |
- g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)), |
- g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))}; |
+ Node* projection1 = NodeProperties::FindProjection(node, 1); |
+ if (projection1) { |
+ // We use UseUniqueRegister here to avoid register sharing with the output |
+ // register. |
+ InstructionOperand inputs[] = { |
+ g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)), |
+ g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))}; |
- InstructionOperand outputs[] = { |
- g.DefineAsRegister(node), |
- g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
+ InstructionOperand outputs[] = { |
+ g.DefineAsRegister(node), |
+ g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
- Emit(kArmSubPair, 2, outputs, 4, inputs); |
+ Emit(kArmSubPair, 2, outputs, 4, inputs); |
+ } else { |
+ // The high word of the result is not used, so we emit the standard 32 bit |
+ // instruction. |
+ Emit(kArmSub | AddressingModeField::encode(kMode_Operand2_R), |
+ g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), |
+ g.UseRegister(node->InputAt(2))); |
+ } |
} |
void InstructionSelector::VisitInt32PairMul(Node* node) { |
ArmOperandGenerator g(this); |
- InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)), |
- g.UseUniqueRegister(node->InputAt(1)), |
- g.UseUniqueRegister(node->InputAt(2)), |
- g.UseUniqueRegister(node->InputAt(3))}; |
- |
- InstructionOperand outputs[] = { |
- g.DefineAsRegister(node), |
- g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
- |
- Emit(kArmMulPair, 2, outputs, 4, inputs); |
-} |
- |
-void InstructionSelector::VisitWord32PairShl(Node* node) { |
- ArmOperandGenerator g(this); |
- // We use g.UseUniqueRegister here for InputAt(0) to guarantee that there is |
- // no register aliasing with output registers. |
- Int32Matcher m(node->InputAt(2)); |
- InstructionOperand shift_operand; |
- if (m.HasValue()) { |
- shift_operand = g.UseImmediate(m.node()); |
+ Node* projection1 = NodeProperties::FindProjection(node, 1); |
+ if (projection1) { |
+ InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)), |
+ g.UseUniqueRegister(node->InputAt(1)), |
+ g.UseUniqueRegister(node->InputAt(2)), |
+ g.UseUniqueRegister(node->InputAt(3))}; |
+ |
+ InstructionOperand outputs[] = { |
+ g.DefineAsRegister(node), |
+ g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
+ |
+ Emit(kArmMulPair, 2, outputs, 4, inputs); |
} else { |
- shift_operand = g.UseUniqueRegister(m.node()); |
+ // The high word of the result is not used, so we emit the standard 32 bit |
+ // instruction. |
+ Emit(kArmMul | AddressingModeField::encode(kMode_Operand2_R), |
+ g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), |
+ g.UseRegister(node->InputAt(2))); |
} |
- |
- InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)), |
- g.UseRegister(node->InputAt(1)), |
- shift_operand}; |
- |
- InstructionOperand outputs[] = { |
- g.DefineAsRegister(node), |
- g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
- |
- Emit(kArmLslPair, 2, outputs, 3, inputs); |
} |
-void InstructionSelector::VisitWord32PairShr(Node* node) { |
- ArmOperandGenerator g(this); |
- // We use g.UseUniqueRegister here for InputAt(1) and InputAt(2) to to |
- // guarantee that there is no register aliasing with output register. |
+namespace { |
+// Shared routine for multiple shift operations. |
+void VisitWord32PairShift(InstructionSelector* selector, InstructionCode opcode, |
+ Node* node) { |
+ ArmOperandGenerator g(selector); |
+ // We use g.UseUniqueRegister here to guarantee that there is |
+ // no register aliasing of input registers with output registers. |
Int32Matcher m(node->InputAt(2)); |
InstructionOperand shift_operand; |
if (m.HasValue()) { |
@@ -1035,38 +1042,37 @@ void InstructionSelector::VisitWord32PairShr(Node* node) { |
shift_operand = g.UseUniqueRegister(m.node()); |
} |
- InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0)), |
+ InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)), |
g.UseUniqueRegister(node->InputAt(1)), |
shift_operand}; |
- InstructionOperand outputs[] = { |
- g.DefineAsRegister(node), |
- g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
+ Node* projection1 = NodeProperties::FindProjection(node, 1); |
- Emit(kArmLsrPair, 2, outputs, 3, inputs); |
-} |
+ InstructionOperand outputs[2]; |
+ InstructionOperand temps[1]; |
+ int32_t output_count = 0; |
+ int32_t temp_count = 0; |
-void InstructionSelector::VisitWord32PairSar(Node* node) { |
- ArmOperandGenerator g(this); |
- // We use g.UseUniqueRegister here for InputAt(1) and InputAt(2) to to |
- // guarantee that there is no register aliasing with output register. |
- Int32Matcher m(node->InputAt(2)); |
- InstructionOperand shift_operand; |
- if (m.HasValue()) { |
- shift_operand = g.UseImmediate(m.node()); |
+ outputs[output_count++] = g.DefineAsRegister(node); |
+ if (projection1) { |
+ outputs[output_count++] = g.DefineAsRegister(projection1); |
} else { |
- shift_operand = g.UseUniqueRegister(m.node()); |
+ temps[temp_count++] = g.TempRegister(); |
} |
- InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0)), |
- g.UseUniqueRegister(node->InputAt(1)), |
- shift_operand}; |
+ selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps); |
+} |
+} // namespace |
+void InstructionSelector::VisitWord32PairShl(Node* node) { |
+ VisitWord32PairShift(this, kArmLslPair, node); |
+} |
- InstructionOperand outputs[] = { |
- g.DefineAsRegister(node), |
- g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
+void InstructionSelector::VisitWord32PairShr(Node* node) { |
+ VisitWord32PairShift(this, kArmLsrPair, node); |
+} |
- Emit(kArmAsrPair, 2, outputs, 3, inputs); |
+void InstructionSelector::VisitWord32PairSar(Node* node) { |
+ VisitWord32PairShift(this, kArmAsrPair, node); |
} |
void InstructionSelector::VisitWord32Ror(Node* node) { |