[v8-dev] ARM: Improve Lithium register constraints.

src/arm/macro-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 34 matching lines @@
       generating_stub_(false),
       allow_stub_calls_(true),
       has_frame_(false) {
   if (isolate() != NULL) {
     code_object_ = Handle<Object>(isolate()->heap()->undefined_value(),
                                   isolate());
   }
 }
 
 
+void MacroAssembler::AddMemOperand(Register dst,
+                                   Register src1,
+                                   const MemOperand& src2,
+                                   SBit s) {
+  ldr(ip, src2);
+  add(dst, src1, Operand(ip), s);
+}
+
+
+void MacroAssembler::SubMemOperand(Register dst,
+                                   Register src1,
+                                   const MemOperand& src2,
+                                   SBit s) {
+  ldr(ip, src2);
+  sub(dst, src1, Operand(ip), s);
+}
+
+
+void MacroAssembler::RsbMemOperand(Register dst,
+                                   Register src1,
+                                   const MemOperand& src2,
+                                   SBit s) {
+  ldr(ip, src2);
+  rsb(dst, src1, Operand(ip), s);
+}
+
+
+void MacroAssembler::AndMemOperand(Register dst,
+                                   Register src1,
+                                   const MemOperand& src2,
+                                   SBit s) {
+  ldr(ip, src2);
+  and_(dst, src1, Operand(ip), s);
+}
+
+
+void MacroAssembler::OrrMemOperand(Register dst,
+                                   Register src1,
+                                   const MemOperand& src2,
+                                   SBit s) {
+  ldr(ip, src2);
+  orr(dst, src1, Operand(ip), s);
+}
+
+
+void MacroAssembler::EorMemOperand(Register dst,
+                                   Register src1,
+                                   const MemOperand& src2,
+                                   SBit s) {
+  ldr(ip, src2);
+  eor(dst, src1, Operand(ip), s);
+}
+
+
 void MacroAssembler::Jump(Register target, Condition cond) {
   bx(target, cond);
 }
 
 
 void MacroAssembler::Jump(intptr_t target, RelocInfo::Mode rmode,
                           Condition cond) {
   mov(ip, Operand(target, rmode));
   bx(ip, cond);
 }
@@ skipping 661 matching lines @@
   // If needed, restore wanted bits of FPSCR.
   Label fpscr_done;
   vmrs(scratch);
   tst(scratch, Operand(kVFPDefaultNaNModeControlBit));
   b(ne, &fpscr_done);
   orr(scratch, scratch, Operand(kVFPDefaultNaNModeControlBit));
   vmsr(scratch);
   bind(&fpscr_done);
 }
 
-void MacroAssembler::VFPCanonicalizeNaN(const DwVfpRegister value,
+void MacroAssembler::VFPCanonicalizeNaN(const DwVfpRegister result,
+                                        const DwVfpRegister value,
                                         const Condition cond) {
-  vsub(value, value, kDoubleRegZero, cond);
+  vsub(result, value, kDoubleRegZero, cond);
 }
 
 
 void MacroAssembler::VFPCompareAndSetFlags(const DwVfpRegister src1,
                                            const DwVfpRegister src2,
                                            const Condition cond) {
   // Compare and move FPSCR flags to the normal condition flags.
   VFPCompareAndLoadFlags(src1, src2, pc, cond);
 }
 
@@ skipping 1301 matching lines @@
                       Heap::kSlicedAsciiStringMapRootIndex,
                       scratch1,
                       scratch2);
 }
 
 
 void MacroAssembler::CompareObjectType(Register object,
                                        Register map,
                                        Register type_reg,
                                        InstanceType type) {
+  const Register temp = type_reg.is(no_reg) ? ip : type_reg;
+
   ldr(map, FieldMemOperand(object, HeapObject::kMapOffset));
-  CompareInstanceType(map, type_reg, type);
+  CompareInstanceType(map, temp, type);
 }
 
 
+void MacroAssembler::CheckObjectTypeRange(Register object,
+                                          Register map,
+                                          InstanceType min_type,
+                                          InstanceType max_type,
+                                          Label* false_label) {
+  STATIC_ASSERT(Map::kInstanceTypeOffset < 4096);
+  STATIC_ASSERT(LAST_TYPE < 256);
+  ldr(map, FieldMemOperand(object, HeapObject::kMapOffset));
+  ldrb(ip, FieldMemOperand(map, Map::kInstanceTypeOffset));
+  sub(ip, ip, Operand(min_type));
+  cmp(ip, Operand(max_type - min_type));
+  b(hi, false_label);
+}
+
+
 void MacroAssembler::CompareInstanceType(Register map,
                                          Register type_reg,
                                          InstanceType type) {
   ldrb(type_reg, FieldMemOperand(map, Map::kInstanceTypeOffset));
   cmp(type_reg, Operand(type));
 }
 
 
 void MacroAssembler::CompareRoot(Register obj,
                                  Heap::RootListIndex index) {
@@ skipping 1813 matching lines @@
 void CodePatcher::EmitCondition(Condition cond) {
   Instr instr = Assembler::instr_at(masm_.pc_);
   instr = (instr & ~kCondMask) | cond;
   masm_.emit(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM