Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(814)

Side by Side Diff: src/ia32/lithium-gap-resolver-ia32.cc

Issue 20070005: Adding Smi support to Add, Sub, Mul, and Bitwise (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Addressed nit Created 7 years, 4 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « src/ia32/lithium-codegen-ia32.cc ('k') | src/ia32/lithium-ia32.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 288 matching lines...) Expand 10 before | Expand all | Expand 10 after
299 Register tmp = EnsureTempRegister(); 299 Register tmp = EnsureTempRegister();
300 Operand dst = cgen_->ToOperand(destination); 300 Operand dst = cgen_->ToOperand(destination);
301 __ mov(tmp, src); 301 __ mov(tmp, src);
302 __ mov(dst, tmp); 302 __ mov(dst, tmp);
303 } 303 }
304 304
305 } else if (source->IsConstantOperand()) { 305 } else if (source->IsConstantOperand()) {
306 LConstantOperand* constant_source = LConstantOperand::cast(source); 306 LConstantOperand* constant_source = LConstantOperand::cast(source);
307 if (destination->IsRegister()) { 307 if (destination->IsRegister()) {
308 Register dst = cgen_->ToRegister(destination); 308 Register dst = cgen_->ToRegister(destination);
309 if (cgen_->IsSmi(constant_source)) { 309 Representation r = cgen_->IsSmi(constant_source)
310 __ Set(dst, cgen_->ToSmiImmediate(constant_source)); 310 ? Representation::Smi() : Representation::Integer32();
311 } else if (cgen_->IsInteger32(constant_source)) { 311 if (cgen_->IsInteger32(constant_source)) {
312 __ Set(dst, cgen_->ToInteger32Immediate(constant_source)); 312 __ Set(dst, cgen_->ToImmediate(constant_source, r));
313 } else { 313 } else {
314 __ LoadObject(dst, cgen_->ToHandle(constant_source)); 314 __ LoadObject(dst, cgen_->ToHandle(constant_source));
315 } 315 }
316 } else if (destination->IsDoubleRegister()) { 316 } else if (destination->IsDoubleRegister()) {
317 double v = cgen_->ToDouble(constant_source); 317 double v = cgen_->ToDouble(constant_source);
318 uint64_t int_val = BitCast<uint64_t, double>(v); 318 uint64_t int_val = BitCast<uint64_t, double>(v);
319 int32_t lower = static_cast<int32_t>(int_val); 319 int32_t lower = static_cast<int32_t>(int_val);
320 int32_t upper = static_cast<int32_t>(int_val >> kBitsPerInt); 320 int32_t upper = static_cast<int32_t>(int_val >> kBitsPerInt);
321 if (CpuFeatures::IsSupported(SSE2)) { 321 if (CpuFeatures::IsSupported(SSE2)) {
322 CpuFeatureScope scope(cgen_->masm(), SSE2); 322 CpuFeatureScope scope(cgen_->masm(), SSE2);
323 XMMRegister dst = cgen_->ToDoubleRegister(destination); 323 XMMRegister dst = cgen_->ToDoubleRegister(destination);
324 if (int_val == 0) { 324 if (int_val == 0) {
325 __ xorps(dst, dst); 325 __ xorps(dst, dst);
326 } else { 326 } else {
327 __ push(Immediate(upper)); 327 __ push(Immediate(upper));
328 __ push(Immediate(lower)); 328 __ push(Immediate(lower));
329 __ movdbl(dst, Operand(esp, 0)); 329 __ movdbl(dst, Operand(esp, 0));
330 __ add(esp, Immediate(kDoubleSize)); 330 __ add(esp, Immediate(kDoubleSize));
331 } 331 }
332 } else { 332 } else {
333 __ push(Immediate(upper)); 333 __ push(Immediate(upper));
334 __ push(Immediate(lower)); 334 __ push(Immediate(lower));
335 X87Register dst = cgen_->ToX87Register(destination); 335 X87Register dst = cgen_->ToX87Register(destination);
336 cgen_->X87Mov(dst, MemOperand(esp, 0)); 336 cgen_->X87Mov(dst, MemOperand(esp, 0));
337 __ add(esp, Immediate(kDoubleSize)); 337 __ add(esp, Immediate(kDoubleSize));
338 } 338 }
339 } else { 339 } else {
340 ASSERT(destination->IsStackSlot()); 340 ASSERT(destination->IsStackSlot());
341 Operand dst = cgen_->ToOperand(destination); 341 Operand dst = cgen_->ToOperand(destination);
342 if (cgen_->IsSmi(constant_source)) { 342 Representation r = cgen_->IsSmi(constant_source)
343 __ Set(dst, cgen_->ToSmiImmediate(constant_source)); 343 ? Representation::Smi() : Representation::Integer32();
344 } else if (cgen_->IsInteger32(constant_source)) { 344 if (cgen_->IsInteger32(constant_source)) {
345 __ Set(dst, cgen_->ToInteger32Immediate(constant_source)); 345 __ Set(dst, cgen_->ToImmediate(constant_source, r));
346 } else { 346 } else {
347 Register tmp = EnsureTempRegister(); 347 Register tmp = EnsureTempRegister();
348 __ LoadObject(tmp, cgen_->ToHandle(constant_source)); 348 __ LoadObject(tmp, cgen_->ToHandle(constant_source));
349 __ mov(dst, tmp); 349 __ mov(dst, tmp);
350 } 350 }
351 } 351 }
352 352
353 } else if (source->IsDoubleRegister()) { 353 } else if (source->IsDoubleRegister()) {
354 if (CpuFeatures::IsSupported(SSE2)) { 354 if (CpuFeatures::IsSupported(SSE2)) {
355 CpuFeatureScope scope(cgen_->masm(), SSE2); 355 CpuFeatureScope scope(cgen_->masm(), SSE2);
(...skipping 184 matching lines...) Expand 10 before | Expand all | Expand 10 after
540 } else if (destination->IsRegister()) { 540 } else if (destination->IsRegister()) {
541 source_uses_[destination->index()] = CountSourceUses(destination); 541 source_uses_[destination->index()] = CountSourceUses(destination);
542 } 542 }
543 } 543 }
544 544
545 #undef __ 545 #undef __
546 546
547 } } // namespace v8::internal 547 } } // namespace v8::internal
548 548
549 #endif // V8_TARGET_ARCH_IA32 549 #endif // V8_TARGET_ARCH_IA32
OLDNEW
« no previous file with comments | « src/ia32/lithium-codegen-ia32.cc ('k') | src/ia32/lithium-ia32.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698