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Side by Side Diff: src/arm/lithium-gap-resolver-arm.cc

Issue 20070005: Adding Smi support to Add, Sub, Mul, and Bitwise (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Addressed nit Created 7 years, 4 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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240 } else { 240 } else {
241 __ ldr(kSavedValueRegister, source_operand); 241 __ ldr(kSavedValueRegister, source_operand);
242 __ str(kSavedValueRegister, destination_operand); 242 __ str(kSavedValueRegister, destination_operand);
243 } 243 }
244 } 244 }
245 245
246 } else if (source->IsConstantOperand()) { 246 } else if (source->IsConstantOperand()) {
247 LConstantOperand* constant_source = LConstantOperand::cast(source); 247 LConstantOperand* constant_source = LConstantOperand::cast(source);
248 if (destination->IsRegister()) { 248 if (destination->IsRegister()) {
249 Register dst = cgen_->ToRegister(destination); 249 Register dst = cgen_->ToRegister(destination);
250 if (cgen_->IsSmi(constant_source)) { 250 Representation r = cgen_->IsSmi(constant_source)
251 __ mov(dst, Operand(cgen_->ToSmi(constant_source))); 251 ? Representation::Smi() : Representation::Integer32();
252 } else if (cgen_->IsInteger32(constant_source)) { 252 if (cgen_->IsInteger32(constant_source)) {
253 __ mov(dst, Operand(cgen_->ToInteger32(constant_source))); 253 __ mov(dst, Operand(cgen_->ToRepresentation(constant_source, r)));
254 } else { 254 } else {
255 __ LoadObject(dst, cgen_->ToHandle(constant_source)); 255 __ LoadObject(dst, cgen_->ToHandle(constant_source));
256 } 256 }
257 } else if (source->IsDoubleRegister()) { 257 } else if (source->IsDoubleRegister()) {
258 DwVfpRegister result = cgen_->ToDoubleRegister(destination); 258 DwVfpRegister result = cgen_->ToDoubleRegister(destination);
259 double v = cgen_->ToDouble(constant_source); 259 double v = cgen_->ToDouble(constant_source);
260 __ Vmov(result, v, ip); 260 __ Vmov(result, v, ip);
261 } else { 261 } else {
262 ASSERT(destination->IsStackSlot()); 262 ASSERT(destination->IsStackSlot());
263 ASSERT(!in_cycle_); // Constant moves happen after all cycles are gone. 263 ASSERT(!in_cycle_); // Constant moves happen after all cycles are gone.
264 if (cgen_->IsSmi(constant_source)) { 264 Representation r = cgen_->IsSmi(constant_source)
265 __ mov(kSavedValueRegister, Operand(cgen_->ToSmi(constant_source))); 265 ? Representation::Smi() : Representation::Integer32();
266 } else if (cgen_->IsInteger32(constant_source)) { 266 if (cgen_->IsInteger32(constant_source)) {
267 __ mov(kSavedValueRegister, 267 __ mov(kSavedValueRegister,
268 Operand(cgen_->ToInteger32(constant_source))); 268 Operand(cgen_->ToRepresentation(constant_source, r)));
269 } else { 269 } else {
270 __ LoadObject(kSavedValueRegister, 270 __ LoadObject(kSavedValueRegister,
271 cgen_->ToHandle(constant_source)); 271 cgen_->ToHandle(constant_source));
272 } 272 }
273 __ str(kSavedValueRegister, cgen_->ToMemOperand(destination)); 273 __ str(kSavedValueRegister, cgen_->ToMemOperand(destination));
274 } 274 }
275 275
276 } else if (source->IsDoubleRegister()) { 276 } else if (source->IsDoubleRegister()) {
277 DwVfpRegister source_register = cgen_->ToDoubleRegister(source); 277 DwVfpRegister source_register = cgen_->ToDoubleRegister(source);
278 if (destination->IsDoubleRegister()) { 278 if (destination->IsDoubleRegister()) {
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309 UNREACHABLE(); 309 UNREACHABLE();
310 } 310 }
311 311
312 moves_[index].Eliminate(); 312 moves_[index].Eliminate();
313 } 313 }
314 314
315 315
316 #undef __ 316 #undef __
317 317
318 } } // namespace v8::internal 318 } } // namespace v8::internal
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