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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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2691 } | 2691 } |
2692 } | 2692 } |
2693 | 2693 |
2694 | 2694 |
2695 // void Simulator::DecodeTypeVFP(Instruction* instr) | 2695 // void Simulator::DecodeTypeVFP(Instruction* instr) |
2696 // The Following ARMv7 VFPv instructions are currently supported. | 2696 // The Following ARMv7 VFPv instructions are currently supported. |
2697 // vmov :Sn = Rt | 2697 // vmov :Sn = Rt |
2698 // vmov :Rt = Sn | 2698 // vmov :Rt = Sn |
2699 // vcvt: Dd = Sm | 2699 // vcvt: Dd = Sm |
2700 // vcvt: Sd = Dm | 2700 // vcvt: Sd = Dm |
| 2701 // vcvt.f64.s32 Dd, Dd, #<fbits> |
2701 // Dd = vabs(Dm) | 2702 // Dd = vabs(Dm) |
2702 // Dd = vneg(Dm) | 2703 // Dd = vneg(Dm) |
2703 // Dd = vadd(Dn, Dm) | 2704 // Dd = vadd(Dn, Dm) |
2704 // Dd = vsub(Dn, Dm) | 2705 // Dd = vsub(Dn, Dm) |
2705 // Dd = vmul(Dn, Dm) | 2706 // Dd = vmul(Dn, Dm) |
2706 // Dd = vdiv(Dn, Dm) | 2707 // Dd = vdiv(Dn, Dm) |
2707 // vcmp(Dd, Dm) | 2708 // vcmp(Dd, Dm) |
2708 // vmrs | 2709 // vmrs |
2709 // Dd = vsqrt(Dm) | 2710 // Dd = vsqrt(Dm) |
2710 void Simulator::DecodeTypeVFP(Instruction* instr) { | 2711 void Simulator::DecodeTypeVFP(Instruction* instr) { |
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2739 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) { | 2740 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) { |
2740 // vneg | 2741 // vneg |
2741 double dm_value = get_double_from_d_register(vm); | 2742 double dm_value = get_double_from_d_register(vm); |
2742 double dd_value = -dm_value; | 2743 double dd_value = -dm_value; |
2743 dd_value = canonicalizeNaN(dd_value); | 2744 dd_value = canonicalizeNaN(dd_value); |
2744 set_d_register_from_double(vd, dd_value); | 2745 set_d_register_from_double(vd, dd_value); |
2745 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { | 2746 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { |
2746 DecodeVCVTBetweenDoubleAndSingle(instr); | 2747 DecodeVCVTBetweenDoubleAndSingle(instr); |
2747 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { | 2748 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { |
2748 DecodeVCVTBetweenFloatingPointAndInteger(instr); | 2749 DecodeVCVTBetweenFloatingPointAndInteger(instr); |
| 2750 } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) && |
| 2751 (instr->Bit(8) == 1)) { |
| 2752 // vcvt.f64.s32 Dd, Dd, #<fbits> |
| 2753 int fraction_bits = 32 - ((instr->Bit(5) << 4) | instr->Bits(3, 0)); |
| 2754 int fixed_value = get_sinteger_from_s_register(vd * 2); |
| 2755 double divide = 1 << fraction_bits; |
| 2756 set_d_register_from_double(vd, fixed_value / divide); |
2749 } else if (((instr->Opc2Value() >> 1) == 0x6) && | 2757 } else if (((instr->Opc2Value() >> 1) == 0x6) && |
2750 (instr->Opc3Value() & 0x1)) { | 2758 (instr->Opc3Value() & 0x1)) { |
2751 DecodeVCVTBetweenFloatingPointAndInteger(instr); | 2759 DecodeVCVTBetweenFloatingPointAndInteger(instr); |
2752 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && | 2760 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && |
2753 (instr->Opc3Value() & 0x1)) { | 2761 (instr->Opc3Value() & 0x1)) { |
2754 DecodeVCMP(instr); | 2762 DecodeVCMP(instr); |
2755 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) { | 2763 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) { |
2756 // vsqrt | 2764 // vsqrt |
2757 double dm_value = get_double_from_d_register(vm); | 2765 double dm_value = get_double_from_d_register(vm); |
2758 double dd_value = sqrt(dm_value); | 2766 double dd_value = sqrt(dm_value); |
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3489 uintptr_t address = *stack_slot; | 3497 uintptr_t address = *stack_slot; |
3490 set_register(sp, current_sp + sizeof(uintptr_t)); | 3498 set_register(sp, current_sp + sizeof(uintptr_t)); |
3491 return address; | 3499 return address; |
3492 } | 3500 } |
3493 | 3501 |
3494 } } // namespace v8::internal | 3502 } } // namespace v8::internal |
3495 | 3503 |
3496 #endif // USE_SIMULATOR | 3504 #endif // USE_SIMULATOR |
3497 | 3505 |
3498 #endif // V8_TARGET_ARCH_ARM | 3506 #endif // V8_TARGET_ARCH_ARM |
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