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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2466 | 2466 |
2467 | 2467 |
2468 void Assembler::vcvt_f32_f64(const SwVfpRegister dst, | 2468 void Assembler::vcvt_f32_f64(const SwVfpRegister dst, |
2469 const DwVfpRegister src, | 2469 const DwVfpRegister src, |
2470 VFPConversionMode mode, | 2470 VFPConversionMode mode, |
2471 const Condition cond) { | 2471 const Condition cond) { |
2472 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); | 2472 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); |
2473 } | 2473 } |
2474 | 2474 |
2475 | 2475 |
| 2476 void Assembler::vcvt_f64_s32(const DwVfpRegister dst, |
| 2477 int fraction_bits, |
| 2478 const Condition cond) { |
| 2479 // Instruction details available in ARM DDI 0406C.b, A8-874. |
| 2480 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 1010(19-16) | Vd(15-12) | |
| 2481 // 101(11-9) | sf=1(8) | sx=1(7) | 1(6) | i(5) | 0(4) | imm4(3-0) |
| 2482 ASSERT(fraction_bits > 0 && fraction_bits <= 32); |
| 2483 ASSERT(CpuFeatures::IsSupported(VFP3)); |
| 2484 int vd, d; |
| 2485 dst.split_code(&vd, &d); |
| 2486 int i = ((32 - fraction_bits) >> 4) & 1; |
| 2487 int imm4 = (32 - fraction_bits) & 0xf; |
| 2488 emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 | |
| 2489 vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4); |
| 2490 } |
| 2491 |
| 2492 |
2476 void Assembler::vneg(const DwVfpRegister dst, | 2493 void Assembler::vneg(const DwVfpRegister dst, |
2477 const DwVfpRegister src, | 2494 const DwVfpRegister src, |
2478 const Condition cond) { | 2495 const Condition cond) { |
2479 // Instruction details available in ARM DDI 0406C.b, A8-968. | 2496 // Instruction details available in ARM DDI 0406C.b, A8-968. |
2480 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) | | 2497 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) | |
2481 // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0) | 2498 // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
2482 int vd, d; | 2499 int vd, d; |
2483 dst.split_code(&vd, &d); | 2500 dst.split_code(&vd, &d); |
2484 int vm, m; | 2501 int vm, m; |
2485 src.split_code(&vm, &m); | 2502 src.split_code(&vm, &m); |
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3084 | 3101 |
3085 // Since a constant pool was just emitted, move the check offset forward by | 3102 // Since a constant pool was just emitted, move the check offset forward by |
3086 // the standard interval. | 3103 // the standard interval. |
3087 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 3104 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
3088 } | 3105 } |
3089 | 3106 |
3090 | 3107 |
3091 } } // namespace v8::internal | 3108 } } // namespace v8::internal |
3092 | 3109 |
3093 #endif // V8_TARGET_ARCH_ARM | 3110 #endif // V8_TARGET_ARCH_ARM |
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