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Side by Side Diff: src/IceAssemblerX86BaseImpl.h

Issue 1428443002: Enhance address mode recovery (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Streamline absolute addressing support (rip-relative on x64) Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=//
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
3 // for details. All rights reserved. Use of this source code is governed by a 3 // for details. All rights reserved. Use of this source code is governed by a
4 // BSD-style license that can be found in the LICENSE file. 4 // BSD-style license that can be found in the LICENSE file.
5 // 5 //
6 // Modified by the Subzero authors. 6 // Modified by the Subzero authors.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // The Subzero Code Generator 10 // The Subzero Code Generator
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3306 } 3306 }
3307 label->bindTo(bound); 3307 label->bindTo(bound);
3308 } 3308 }
3309 3309
3310 template <class Machine> 3310 template <class Machine>
3311 void AssemblerX86Base<Machine>::emitOperand( 3311 void AssemblerX86Base<Machine>::emitOperand(
3312 int rm, const typename Traits::Operand &operand) { 3312 int rm, const typename Traits::Operand &operand) {
3313 assert(rm >= 0 && rm < 8); 3313 assert(rm >= 0 && rm < 8);
3314 const intptr_t length = operand.length_; 3314 const intptr_t length = operand.length_;
3315 assert(length > 0); 3315 assert(length > 0);
3316 intptr_t displacement_start = 1;
3316 // Emit the ModRM byte updated with the given RM value. 3317 // Emit the ModRM byte updated with the given RM value.
3317 assert((operand.encoding_[0] & 0x38) == 0); 3318 assert((operand.encoding_[0] & 0x38) == 0);
3318 emitUint8(operand.encoding_[0] + (rm << 3)); 3319 emitUint8(operand.encoding_[0] + (rm << 3));
3320 // Whenever the addressing mode is not register indirect, using esp == 0x4
3321 // as the register operation indicates an SIB byte follows.
3322 if (((operand.encoding_[0] & 0xc0) != 0xc0) &&
3323 ((operand.encoding_[0] & 0x07) == 0x04)) {
3324 emitUint8(operand.encoding_[1]);
3325 displacement_start = 2;
3326 }
3327 // Emit the displacement and the fixup that affects it, if any.
3319 if (operand.fixup()) { 3328 if (operand.fixup()) {
3320 emitFixup(operand.fixup()); 3329 emitFixup(operand.fixup());
3330 assert(length - displacement_start == 4);
3321 } 3331 }
3322 // Emit the rest of the encoded operand. 3332 for (intptr_t i = displacement_start; i < length; i++) {
3323 for (intptr_t i = 1; i < length; i++) {
3324 emitUint8(operand.encoding_[i]); 3333 emitUint8(operand.encoding_[i]);
3325 } 3334 }
3326 } 3335 }
3327 3336
3328 template <class Machine> 3337 template <class Machine>
3329 void AssemblerX86Base<Machine>::emitImmediate(Type Ty, const Immediate &imm) { 3338 void AssemblerX86Base<Machine>::emitImmediate(Type Ty, const Immediate &imm) {
3330 if (Ty == IceType_i16) { 3339 if (Ty == IceType_i16) {
3331 assert(!imm.fixup()); 3340 assert(!imm.fixup());
3332 emitInt16(imm.value()); 3341 emitInt16(imm.value());
3333 } else { 3342 } else {
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3437 (void)shifter; 3446 (void)shifter;
3438 if (Ty == IceType_i16) 3447 if (Ty == IceType_i16)
3439 emitOperandSizeOverride(); 3448 emitOperandSizeOverride();
3440 emitRexB(Ty, operand.rm()); 3449 emitRexB(Ty, operand.rm());
3441 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); 3450 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3);
3442 emitOperand(rm, operand); 3451 emitOperand(rm, operand);
3443 } 3452 }
3444 3453
3445 } // end of namespace X86Internal 3454 } // end of namespace X86Internal
3446 } // end of namespace Ice 3455 } // end of namespace Ice
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