Handle MOV (immediate) and MOVT to load ARM global addresses.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 26 matching lines @@
 
 namespace Ice {
 namespace ARM32 {
 
 /// Encoding of an ARM 32-bit instruction.
 using IValueT = uint32_t;
 
 /// An Offset value (+/-) used in an ARM 32-bit instruction.
 using IOffsetT = int32_t;
 
+/// Handles encoding of bottom/top 16 bits of an address using movw/movt.
+class MoveRelocatableFixup : public AssemblerFixup {
+  MoveRelocatableFixup &operator=(const MoveRelocatableFixup &) = delete;
+  MoveRelocatableFixup(const MoveRelocatableFixup &) = default;
+
+public:
+  MoveRelocatableFixup() = default;
+  size_t emit(GlobalContext *Ctx, const Assembler &Asm) const override;
+};
+
 class AssemblerARM32 : public Assembler {
   AssemblerARM32() = delete;
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
 public:
   explicit AssemblerARM32(GlobalContext *Ctx, bool use_far_branches = false)
       : Assembler(Asm_ARM32, Ctx) {
     // TODO(kschimpf): Add mode if needed when branches are handled.
     (void)use_far_branches;
   }
   ~AssemblerARM32() override {
     if (BuildDefs::asserts()) {
       for (const Label *Label : CfgNodeLabels) {
         Label->finalCheck();
       }
       for (const Label *Label : LocalLabels) {
         Label->finalCheck();
       }
     }
   }
 
+  MoveRelocatableFixup *createMoveFixup(bool IsMovW, const Constant *Value);
+
   void alignFunction() override {
     const SizeT Align = 1 << getBundleAlignLog2Bytes();
     SizeT BytesNeeded = Utils::OffsetToAlignment(Buffer.getPosition(), Align);
     constexpr IValueT UndefinedInst = 0xe7fedef0; // udf #60896
     constexpr SizeT InstSize = sizeof(IValueT);
     assert(BytesNeeded % InstSize == 0);
     while (BytesNeeded > 0) {
       AssemblerBuffer::EnsureCapacity ensured(&Buffer);
       emitInst(UndefinedInst);
       BytesNeeded -= InstSize;
@@ skipping 52 matching lines @@
            bool SetFlags, CondARM32::Cond Cond);
 
   void b(Label *L, CondARM32::Cond Cond);
 
   void bkpt(uint16_t Imm16);
 
   void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
   void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
+  void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+
+  void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+
   void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
 
   void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
@@ skipping 33 matching lines @@
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H