Add ADC (immediate) instruction to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 243 matching lines @@
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   AssemblerFixup *F = createTextFixup(Text, InstSize);
   emitFixup(F);
   for (SizeT I = 0; I < InstSize; ++I)
     Buffer.emit<char>(0);
 }
 
 void ARM32::AssemblerARM32::emitType01(CondARM32::Cond Cond, uint32_t Type,
                                        uint32_t Opcode, bool SetCc, uint32_t Rn,
                                        uint32_t Rd, uint32_t Imm12) {
-  assert(isGPRRegisterDefined(Rd));
-  // TODO(kschimpf): Remove void cast when MINIMAL build allows.
-  (void)isGPRRegisterDefined(Rd);
-  assert(Cond != CondARM32::kNone);
+  if (!isGPRRegisterDefined(Rd) || !isConditionDefined(Cond))
+    return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const uint32_t Encoding = (encodeCondition(Cond) << kConditionShift) |
                             (Type << kTypeShift) | (Opcode << kOpcodeShift) |
                             (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
                             (Rd << kRdShift) | Imm12;
   emitInst(Encoding);
 }
 
 void ARM32::AssemblerARM32::emitMemOp(CondARM32::Cond Cond, uint32_t InstType,
                                       bool IsLoad, bool IsByte, uint32_t Rt,
                                       uint32_t Address) {
-  assert(isGPRRegisterDefined(Rt));
-  assert(Cond != CondARM32::kNone);
+  if (!isGPRRegisterDefined(Rt) || !isConditionDefined(Cond))
+    return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const uint32_t Encoding = (encodeCondition(Cond) << kConditionShift) |
                             (InstType << kTypeShift) | (IsLoad ? L : 0) |
                             (IsByte ? B : 0) | (Rt << kRdShift) | Address;
   emitInst(Encoding);
 }
 
+void ARM32::AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
+                                const Operand *OpSrc1, bool SetFlags,
+                                CondARM32::Cond Cond) {
+  uint32_t Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  uint32_t Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  constexpr uint32_t Adc = B2 | B0; // 0101
+  uint32_t Src1Value;
+  // TODO(kschimpf) Other possible decodings of adc.
+  switch (decodeOperand(OpSrc1, Src1Value)) {
+  default:
+    return setNeedsTextFixup();
+  case DecodedAsRotatedImm8: {
+    // ADC (Immediated) = ARM section A8.8.1, encoding A1:
+    //   adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
+    //
+    // cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+    if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataImmediate, Adc, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  };
+}
+
 void ARM32::AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
                                 const Operand *OpSrc1, bool SetFlags,
                                 CondARM32::Cond Cond) {
   uint32_t Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   uint32_t Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   constexpr uint32_t Add = B2; // 0100
@@ skipping 196 matching lines @@
     if (Rd == RegARM32::Encoded_Reg_pc)
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace Ice