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Side by Side Diff: unittest/AssemblerX8632/GPRArith.cpp

Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Add some comments Created 5 years, 1 month ago
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1 //===- subzero/unittest/AssemblerX8632/GPRArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8632/GPRArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8632/TestUtil.h" 9 #include "AssemblerX8632/TestUtil.h"
10 10
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
48 #define TestSetCC(C, Src0, Value0, Src1, Value1, Dest, IsTrue) \ 48 #define TestSetCC(C, Src0, Value0, Src1, Value1, Dest, IsTrue) \
49 do { \ 49 do { \
50 const uint32_t T0 = allocateDword(); \ 50 const uint32_t T0 = allocateDword(); \
51 constexpr uint32_t V0 = 0xF00F00; \ 51 constexpr uint32_t V0 = 0xF00F00; \
52 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src0, Immediate(Value0)); \ 52 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src0, Immediate(Value0)); \
53 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src1, Immediate(Value1)); \ 53 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src1, Immediate(Value1)); \
54 __ cmp(IceType_i32, GPRRegister::Encoded_Reg_##Src0, \ 54 __ cmp(IceType_i32, GPRRegister::Encoded_Reg_##Src0, \
55 GPRRegister::Encoded_Reg_##Src1); \ 55 GPRRegister::Encoded_Reg_##Src1); \
56 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Dest, Immediate(0)); \ 56 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Dest, Immediate(0)); \
57 __ setcc(Cond::Br_##C, \ 57 __ setcc(Cond::Br_##C, \
58 RegX8632::getEncodedByteReg(GPRRegister::Encoded_Reg_##Dest)); \ 58 RegX8632::getEncodedGPR(GPRRegister::Encoded_Reg_##Dest)); \
59 __ setcc(Cond::Br_##C, dwordAddress(T0)); \ 59 __ setcc(Cond::Br_##C, dwordAddress(T0)); \
60 \ 60 \
61 AssembledTest test = assemble(); \ 61 AssembledTest test = assemble(); \
62 test.setDwordTo(T0, V0); \ 62 test.setDwordTo(T0, V0); \
63 \ 63 \
64 test.run(); \ 64 test.run(); \
65 \ 65 \
66 EXPECT_EQ(IsTrue, test.Dest()) \ 66 EXPECT_EQ(IsTrue, test.Dest()) \
67 << "(" #C ", " #Src0 ", " #Value0 ", " #Src1 ", " #Value1 ", " #Dest \ 67 << "(" #C ", " #Src0 ", " #Value0 ", " #Src1 ", " #Value1 ", " #Dest \
68 ", " #IsTrue ")"; \ 68 ", " #IsTrue ")"; \
(...skipping 1671 matching lines...) Expand 10 before | Expand all | Expand 10 after
1740 TEST_F(AssemblerX8632Test, Bt) { 1740 TEST_F(AssemblerX8632Test, Bt) {
1741 #define TestImpl(Dst, Value0, Src, Value1) \ 1741 #define TestImpl(Dst, Value0, Src, Value1) \
1742 do { \ 1742 do { \
1743 static constexpr char TestString[] = \ 1743 static constexpr char TestString[] = \
1744 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ")"; \ 1744 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ")"; \
1745 static constexpr uint32_t Expected = ((Value0) & (1u << (Value1))) != 0; \ 1745 static constexpr uint32_t Expected = ((Value0) & (1u << (Value1))) != 0; \
1746 \ 1746 \
1747 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Dst, Immediate(Value0)); \ 1747 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Dst, Immediate(Value0)); \
1748 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src, Immediate(Value1)); \ 1748 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src, Immediate(Value1)); \
1749 __ bt(GPRRegister::Encoded_Reg_##Dst, GPRRegister::Encoded_Reg_##Src); \ 1749 __ bt(GPRRegister::Encoded_Reg_##Dst, GPRRegister::Encoded_Reg_##Src); \
1750 __ setcc(Cond::Br_b, ByteRegister::Encoded_Reg_al); \ 1750 __ setcc(Cond::Br_b, GPRRegister::Encoded_Reg_al); \
1751 __ And(IceType_i32, GPRRegister::Encoded_Reg_eax, Immediate(0xFFu)); \ 1751 __ And(IceType_i32, GPRRegister::Encoded_Reg_eax, Immediate(0xFFu)); \
1752 \ 1752 \
1753 AssembledTest test = assemble(); \ 1753 AssembledTest test = assemble(); \
1754 test.run(); \ 1754 test.run(); \
1755 \ 1755 \
1756 ASSERT_EQ(Expected, test.eax()) << TestString; \ 1756 ASSERT_EQ(Expected, test.eax()) << TestString; \
1757 reset(); \ 1757 reset(); \
1758 } while (0) 1758 } while (0)
1759 1759
1760 TestImpl(eax, 0x08000000, ebx, 27u); 1760 TestImpl(eax, 0x08000000, ebx, 27u);
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1875 #undef TestImplValue 1875 #undef TestImplValue
1876 #undef TestImplSize 1876 #undef TestImplSize
1877 #undef TestImplRegAddr 1877 #undef TestImplRegAddr
1878 #undef TestImplRegReg 1878 #undef TestImplRegReg
1879 } 1879 }
1880 1880
1881 } // end of anonymous namespace 1881 } // end of anonymous namespace
1882 } // end of namespace Test 1882 } // end of namespace Test
1883 } // end of namespace X8632 1883 } // end of namespace X8632
1884 } // end of namespace Ice 1884 } // end of namespace Ice
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