Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 188 matching lines @@
   this->addSource(Source);
 }
 
 template <class Machine>
 InstX86Cmpxchg<Machine>::InstX86Cmpxchg(Cfg *Func, Operand *DestOrAddr,
                                         Variable *Eax, Variable *Desired,
                                         bool Locked)
     : InstX86BaseLockable<Machine>(Func, InstX86Base<Machine>::Cmpxchg, 3,
                                    llvm::dyn_cast<Variable>(DestOrAddr),
                                    Locked) {
-  assert(Eax->getRegNum() ==
+  assert(InstX86Base<Machine>::Traits::getBaseReg(Eax->getRegNum()) ==
          InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
   this->addSource(DestOrAddr);
   this->addSource(Eax);
   this->addSource(Desired);
 }
 
 template <class Machine>
 InstX86Cmpxchg8b<Machine>::InstX86Cmpxchg8b(
     Cfg *Func, typename InstX86Base<Machine>::Traits::X86OperandMem *Addr,
     Variable *Edx, Variable *Eax, Variable *Ecx, Variable *Ebx, bool Locked)
@@ skipping 294 matching lines @@
   Str << "\tjmp\t*";
   getJmpTarget()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Jmp<Machine>::emitIAS(const Cfg *Func) const {
   // Note: Adapted (mostly copied) from InstX86Call<Machine>::emitIAS().
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Operand *Target = getJmpTarget();
-  if (const auto Var = llvm::dyn_cast<Variable>(Target)) {
+  if (const auto *Var = llvm::dyn_cast<Variable>(Target)) {
     if (Var->hasReg()) {
-      Asm->jmp(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          Var->getRegNum()));
+      Asm->jmp(InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum()));
     } else {
       // The jmp instruction with a memory operand should be possible to
       // encode, but it isn't a valid sandboxed instruction, and there
       // shouldn't be a register allocation issue to jump through a scratch
       // register, so we don't really need to bother implementing it.
       llvm::report_fatal_error("Assembler can't jmp to memory operand");
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(
                  Target)) {
     (void)Mem;
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     llvm::report_fatal_error("Assembler can't jmp to memory operand");
-  } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
+  } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
     assert(CR->getOffset() == 0 && "We only support jumping to a function");
     Asm->jmp(CR);
-  } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
     // NaCl trampoline calls refer to an address within the sandbox directly.
     // This is usually only needed for non-IRT builds and otherwise not very
     // portable or stable. Usually this is only done for "calls" and not jumps.
     // TODO(jvoung): Support this when there is a lowering that actually
     // triggers this case.
     (void)Imm;
     llvm::report_fatal_error("Unexpected jmp to absolute address");
   } else {
     llvm::report_fatal_error("Unexpected operand type");
   }
 }
 
 template <class Machine> void InstX86Jmp<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "jmp ";
   getJmpTarget()->dump(Func);
 }
 
 template <class Machine>
 void InstX86Call<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Str << "\tcall\t";
-  if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getCallTarget())) {
+  if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getCallTarget())) {
     // Emit without a leading '$'.
     Str << CI->getValue();
   } else if (const auto CallTarget =
                  llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
     CallTarget->emitWithoutPrefix(Func->getTarget());
   } else {
     Str << "*";
     getCallTarget()->emit(Func);
   }
   Func->getTarget()->resetStackAdjustment();
 }
 
 template <class Machine>
 void InstX86Call<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Operand *Target = getCallTarget();
-  if (const auto Var = llvm::dyn_cast<Variable>(Target)) {
+  if (const auto *Var = llvm::dyn_cast<Variable>(Target)) {
     if (Var->hasReg()) {
-      Asm->call(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          Var->getRegNum()));
+      Asm->call(InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum()));
     } else {
       Asm->call(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(Var));
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(
                  Target)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     Asm->call(Mem->toAsmAddress(Asm));
-  } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
+  } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
     assert(CR->getOffset() == 0 && "We only support calling a function");
     Asm->call(CR);
-  } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
     Asm->call(Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
   Func->getTarget()->resetStackAdjustment();
 }
 
 template <class Machine>
 void InstX86Call<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   if (this->getDest()) {
     this->dumpDest(Func);
     Str << " = ";
   }
   Str << "call ";
   getCallTarget()->dump(Func);
 }
 
-// The ShiftHack parameter is used to emit "cl" instead of "ecx" for shift
-// instructions, in order to be syntactically valid. The this->Opcode parameter
-// needs to be char* and not IceString because of template issues.
+// The this->Opcode parameter needs to be char* and not IceString because of
+// template issues.
 template <class Machine>
 void InstX86Base<Machine>::emitTwoAddress(const char *Opcode, const Inst *Inst,
-                                          const Cfg *Func, bool ShiftHack) {
+                                          const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Operand *Dest = Inst->getDest();
   if (Dest == nullptr)
     Dest = Inst->getSrc(0);
   assert(Dest == Inst->getSrc(0));
   Operand *Src1 = Inst->getSrc(1);
   Str << "\t" << Opcode << InstX86Base<Machine>::getWidthString(Dest->getType())
       << "\t";
-  const auto ShiftReg = llvm::dyn_cast<Variable>(Src1);
-  if (ShiftHack && ShiftReg &&
-      ShiftReg->getRegNum() ==
-          InstX86Base<Machine>::Traits::RegisterSet::Reg_ecx)
-    Str << "%cl";
-  else
-    Src1->emit(Func);
+  Src1->emit(Func);
   Str << ", ";
   Dest->emit(Func);
 }
 
 template <class Machine>
 void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op,
                     const typename InstX86Base<
                         Machine>::Traits::Assembler::GPREmitterOneOp &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
-  if (const auto Var = llvm::dyn_cast<Variable>(Op)) {
+  if (const auto *Var = llvm::dyn_cast<Variable>(Op)) {
     if (Var->hasReg()) {
       // We cheat a little and use GPRRegister even for byte operations.
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister VarReg =
-          InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
-              Ty, Var->getRegNum());
+          InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum());
       (Asm->*(Emitter.Reg))(Ty, VarReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(Var));
       (Asm->*(Emitter.Addr))(Ty, StackAddr);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Op)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Asm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, bool VarCanBeByte, bool SrcCanBeByte>
 void emitIASRegOpTyGPR(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterRegOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister VarReg =
       VarCanBeByte
-          ? InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
-                Ty, Var->getRegNum())
-          : InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                Var->getRegNum());
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+          ? InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum())
+          : InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum());
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
           SrcCanBeByte
-              ? InstX86Base<Machine>::Traits::RegisterSet::
-                    getEncodedByteRegOrGPR(Ty, SrcVar->getRegNum())
-              : InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
+              ? InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum())
+              : InstX86Base<Machine>::Traits::getEncodedGPR(
                     SrcVar->getRegNum());
       (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
-  } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
-  } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
+  } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     AssemblerFixup *Fixup =
         Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Reloc->getOffset(), Fixup));
-  } else if (const auto Split = llvm::dyn_cast<
+  } else if (const auto *Split = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::VariableSplit>(Src)) {
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAddrOpTyGPR(
     const Cfg *Func, Type Ty,
     const typename InstX86Base<Machine>::Traits::Address &Addr,
     const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // Src can only be Reg or Immediate.
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
-            Ty, SrcVar->getRegNum());
+        InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum());
     (Asm->*(Emitter.AddrGPR))(Ty, Addr, SrcReg);
-  } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.AddrImm))(Ty, Addr, Immediate(Imm->getValue()));
-  } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
+  } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     AssemblerFixup *Fixup =
         Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
     (Asm->*(Emitter.AddrImm))(Ty, Addr, Immediate(Reloc->getOffset(), Fixup));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAsAddrOpTyGPR(
     const Cfg *Func, Type Ty, const Operand *Op0, const Operand *Op1,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
         &Emitter) {
-  if (const auto Op0Var = llvm::dyn_cast<Variable>(Op0)) {
+  if (const auto *Op0Var = llvm::dyn_cast<Variable>(Op0)) {
     assert(!Op0Var->hasReg());
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(Op0Var));
     emitIASAddrOpTyGPR<Machine>(Func, Ty, StackAddr, Op1, Emitter);
-  } else if (const auto Op0Mem = llvm::dyn_cast<
+  } else if (const auto *Op0Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Op0)) {
     typename InstX86Base<Machine>::Traits::Assembler *Asm =
         Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
     Op0Mem->emitSegmentOverride(Asm);
     emitIASAddrOpTyGPR<Machine>(Func, Ty, Op0Mem->toAsmAddress(Asm), Op1,
                                 Emitter);
-  } else if (const auto Split = llvm::dyn_cast<
+  } else if (const auto *Split = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::VariableSplit>(Op0)) {
     emitIASAddrOpTyGPR<Machine>(Func, Ty, Split->toAsmAddress(Func), Op1,
                                 Emitter);
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void InstX86Base<Machine>::emitIASGPRShift(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterShiftOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // Technically, the Dest Var can be mem as well, but we only use Reg. We can
   // extend this to check Dest if we decide to use that form.
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister VarReg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
-          Ty, Var->getRegNum());
+      InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum());
   // Src must be reg == ECX or an Imm8. This is asserted by the assembler.
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
-            Ty, SrcVar->getRegNum());
+        InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum());
     (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
-  } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASGPRShiftDouble(
     const Cfg *Func, const Variable *Dest, const Operand *Src1Op,
     const Operand *Src2Op,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterShiftD
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // Dest can be reg or mem, but we only use the reg variant.
   assert(Dest->hasReg());
   typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister DestReg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          Dest->getRegNum());
+      InstX86Base<Machine>::Traits::getEncodedGPR(Dest->getRegNum());
   // SrcVar1 must be reg.
-  const auto SrcVar1 = llvm::cast<Variable>(Src1Op);
+  const auto *SrcVar1 = llvm::cast<Variable>(Src1Op);
   assert(SrcVar1->hasReg());
   typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          SrcVar1->getRegNum());
+      InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar1->getRegNum());
   Type Ty = SrcVar1->getType();
   // Src2 can be the implicit CL register or an immediate.
-  if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src2Op)) {
+  if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2Op)) {
     (Asm->*(Emitter.GPRGPRImm))(Ty, DestReg, SrcReg,
                                 Immediate(Imm->getValue()));
   } else {
     assert(llvm::cast<Variable>(Src2Op)->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_ecx);
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_cl);
     (Asm->*(Emitter.GPRGPR))(Ty, DestReg, SrcReg);
   }
 }
 
 template <class Machine>
 void emitIASXmmShift(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterShiftOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Var->hasReg());
   typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister VarReg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-          Var->getRegNum());
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+      InstX86Base<Machine>::Traits::getEncodedXmm(Var->getRegNum());
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
-          InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-              SrcVar->getRegNum());
+          InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
       (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
-  } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.XmmImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASRegOpTyXMM(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Var->hasReg());
   typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister VarReg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-          Var->getRegNum());
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+      InstX86Base<Machine>::Traits::getEncodedXmm(Var->getRegNum());
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
-          InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-              SrcVar->getRegNum());
+          InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
       (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
-  } else if (const auto Imm = llvm::dyn_cast<Constant>(Src)) {
+  } else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
     (Asm->*(Emitter.XmmAddr))(
         Ty, VarReg,
         InstX86Base<Machine>::Traits::Address::ofConstPool(Asm, Imm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, typename DReg_t, typename SReg_t,
           DReg_t (*destEnc)(int32_t), SReg_t (*srcEnc)(int32_t)>
 void emitIASCastRegOp(const Cfg *Func, Type DestTy, const Variable *Dest,
                       Type SrcTy, const Operand *Src,
                       const typename InstX86Base<Machine>::Traits::Assembler::
                           template CastEmitterRegOp<DReg_t, SReg_t> &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
       (Asm->*(Emitter.RegReg))(DestTy, DestReg, SrcTy, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, Mem->toAsmAddress(Asm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, typename DReg_t, typename SReg_t,
           DReg_t (*destEnc)(int32_t), SReg_t (*srcEnc)(int32_t)>
 void emitIASThreeOpImmOps(
     const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src0,
     const Operand *Src1,
     const typename InstX86Base<Machine>::Traits::Assembler::
         template ThreeOpImmEmitter<DReg_t, SReg_t> Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // This only handles Dest being a register, and Src1 being an immediate.
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
   Immediate Imm(llvm::cast<ConstantInteger32>(Src1)->getValue());
-  if (const auto SrcVar = llvm::dyn_cast<Variable>(Src0)) {
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar->hasReg()) {
       SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
       (Asm->*(Emitter.RegRegImm))(DispatchTy, DestReg, SrcReg, Imm);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, SrcStackAddr, Imm);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src0)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, Mem->toAsmAddress(Asm),
                                  Imm);
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASMovlikeXMM(
     const Cfg *Func, const Variable *Dest, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterMovOps
         Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (Dest->hasReg()) {
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-            Dest->getRegNum());
-    if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
+        InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum());
+    if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
       if (SrcVar->hasReg()) {
         (Asm->*(Emitter.XmmXmm))(
-            DestReg, InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                         SrcVar->getRegNum()));
+            DestReg,
+            InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
       } else {
         typename InstX86Base<Machine>::Traits::Address StackAddr(
             static_cast<typename InstX86Base<Machine>::Traits::TargetLowering
                             *>(Func->getTarget())
                 ->stackVarToAsmOperand(SrcVar));
         (Asm->*(Emitter.XmmAddr))(DestReg, StackAddr);
       }
-    } else if (const auto SrcMem = llvm::dyn_cast<
+    } else if (const auto *SrcMem = llvm::dyn_cast<
                    typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
       assert(SrcMem->getSegmentRegister() ==
              InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
       (Asm->*(Emitter.XmmAddr))(DestReg, SrcMem->toAsmAddress(Asm));
     } else {
       llvm_unreachable("Unexpected operand type");
     }
   } else {
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(Dest));
     // Src must be a register in this case.
-    const auto SrcVar = llvm::cast<Variable>(Src);
+    const auto *SrcVar = llvm::cast<Variable>(Src);
     assert(SrcVar->hasReg());
     (Asm->*(Emitter.AddrXmm))(
-        StackAddr, InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                       SrcVar->getRegNum()));
+        StackAddr,
+        InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
   }
 }
 
 template <class Machine>
 void InstX86Sqrtss<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Type Ty = this->getSrc(0)->getType();
@@ skipping 244 matching lines @@
 
 template <class Machine>
 void InstX86Imul<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 2);
   Variable *Dest = this->getDest();
   if (isByteSizedArithType(Dest->getType())) {
     // The 8-bit version of imul only allows the form "imul r/m8".
-    const auto Src0Var = llvm::dyn_cast<Variable>(this->getSrc(0));
+    const auto *Src0Var = llvm::dyn_cast<Variable>(this->getSrc(0));
     (void)Src0Var;
-    assert(Src0Var &&
-           Src0Var->getRegNum() ==
-               InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
+    assert(Src0Var->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_al);
     Str << "\timulb\t";
     this->getSrc(1)->emit(Func);
   } else if (llvm::isa<Constant>(this->getSrc(1))) {
     Str << "\timul" << this->getWidthString(Dest->getType()) << "\t";
     this->getSrc(1)->emit(Func);
     Str << ", ";
     this->getSrc(0)->emit(Func);
     Str << ", ";
     Dest->emit(Func);
   } else {
     this->emitTwoAddress("imul", this, Func);
   }
 }
 
 template <class Machine>
 void InstX86Imul<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   const Variable *Var = this->getDest();
   Type Ty = Var->getType();
   const Operand *Src = this->getSrc(1);
   if (isByteSizedArithType(Ty)) {
     // The 8-bit version of imul only allows the form "imul r/m8".
-    const auto Src0Var = llvm::dyn_cast<Variable>(this->getSrc(0));
+    const auto *Src0Var = llvm::dyn_cast<Variable>(this->getSrc(0));
     (void)Src0Var;
-    assert(Src0Var &&
-           Src0Var->getRegNum() ==
-               InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
+    assert(Src0Var->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_al);
     static const typename InstX86Base<
         Machine>::Traits::Assembler::GPREmitterOneOp Emitter = {
         &InstX86Base<Machine>::Traits::Assembler::imul,
         &InstX86Base<Machine>::Traits::Assembler::imul};
     emitIASOpTyGPR<Machine>(Func, Ty, this->getSrc(1), Emitter);
   } else {
     // The two-address version is used when multiplying by a non-constant
     // or doing an 8-bit multiply.
     assert(Var == this->getSrc(0));
     static const typename InstX86Base<
@@ skipping 30 matching lines @@
   assert(llvm::isa<Constant>(this->getSrc(1)));
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::imul,
                      &InstX86Base<Machine>::Traits::Assembler::imul};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR>(
+      InstX86Base<Machine>::Traits::getEncodedGPR,
+      InstX86Base<Machine>::Traits::getEncodedGPR>(
       Func, Ty, Dest, this->getSrc(0), this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Insertps<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Func->getTarget())
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   const Variable *Dest = this->getDest();
   assert(Dest == this->getSrc(0));
   Type Ty = Dest->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::insertps,
                      &InstX86Base<Machine>::Traits::Assembler::insertps};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm>(
+      InstX86Base<Machine>::Traits::getEncodedXmm,
+      InstX86Base<Machine>::Traits::getEncodedXmm>(
       Func, Ty, Dest, this->getSrc(1), this->getSrc(2), Emitter);
 }
 
 template <class Machine>
 void InstX86Cbwdq<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Operand *Src0 = this->getSrc(0);
   assert(llvm::isa<Variable>(Src0));
-  assert(llvm::cast<Variable>(Src0)->getRegNum() ==
-         InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
   switch (Src0->getType()) {
   default:
     llvm_unreachable("unexpected source type!");
     break;
   case IceType_i8:
+    assert(llvm::cast<Variable>(Src0)->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_al);
     assert(this->getDest()->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_ax);
     Str << "\t"
         << "cbtw";
     break;
   case IceType_i16:
+    assert(llvm::cast<Variable>(Src0)->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_ax);
     assert(this->getDest()->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_dx);
     Str << "\t"
         << "cwtd";
     break;
   case IceType_i32:
+    assert(llvm::cast<Variable>(Src0)->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Str << "\t"
         << "cltd";
     break;
   case IceType_i64:
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Str << "\t"
         << "cdto";
     break;
   }
 }
 
 template <class Machine>
 void InstX86Cbwdq<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   Operand *Src0 = this->getSrc(0);
   assert(llvm::isa<Variable>(Src0));
-  assert(llvm::cast<Variable>(Src0)->getRegNum() ==
-         InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
   switch (Src0->getType()) {
   default:
     llvm_unreachable("unexpected source type!");
     break;
   case IceType_i8:
+    assert(llvm::cast<Variable>(Src0)->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_al);
     assert(this->getDest()->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_ax);
     Asm->cbw();
     break;
   case IceType_i16:
+    assert(llvm::cast<Variable>(Src0)->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_ax);
     assert(this->getDest()->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_dx);
     Asm->cwd();
     break;
   case IceType_i32:
+    assert(llvm::cast<Variable>(Src0)->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Asm->cdq();
     break;
   case IceType_i64:
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Asm->cqo();
     break;
   }
@@ skipping 42 matching lines @@
 
 template <class Machine>
 void InstX86Shld<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = this->getDest();
   assert(this->getSrcSize() == 3);
   assert(Dest == this->getSrc(0));
   Str << "\tshld" << this->getWidthString(Dest->getType()) << "\t";
-  if (const auto ShiftReg = llvm::dyn_cast<Variable>(this->getSrc(2))) {
-    (void)ShiftReg;
-    assert(ShiftReg->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_ecx);
-    Str << "%cl";
-  } else {
-    this->getSrc(2)->emit(Func);
-  }
+  this->getSrc(2)->emit(Func);
   Str << ", ";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   Dest->emit(Func);
 }
 
 template <class Machine>
 void InstX86Shld<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
@@ skipping 19 matching lines @@
 
 template <class Machine>
 void InstX86Shrd<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = this->getDest();
   assert(this->getSrcSize() == 3);
   assert(Dest == this->getSrc(0));
   Str << "\tshrd" << this->getWidthString(Dest->getType()) << "\t";
-  if (const auto ShiftReg = llvm::dyn_cast<Variable>(this->getSrc(2))) {
-    (void)ShiftReg;
-    assert(ShiftReg->getRegNum() ==
-           InstX86Base<Machine>::Traits::RegisterSet::Reg_ecx);
-    Str << "%cl";
-  } else {
-    this->getSrc(2)->emit(Func);
-  }
+  this->getSrc(2)->emit(Func);
   Str << ", ";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   Dest->emit(Func);
 }
 
 template <class Machine>
 void InstX86Shrd<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
@@ skipping 40 matching lines @@
   assert(this->getDest()->hasReg());
   assert(this->getSrcSize() == 2);
   Operand *Src = this->getSrc(1);
   Type SrcTy = Src->getType();
   assert(SrcTy == IceType_i16 || SrcTy == IceType_i32 ||
          (InstX86Base<Machine>::Traits::Is64Bit));
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
-      Asm->cmov(SrcTy, Condition,
-                InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                    this->getDest()->getRegNum()),
-                InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                    SrcVar->getRegNum()));
+      Asm->cmov(
+          SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
+                                this->getDest()->getRegNum()),
+          InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum()));
     } else {
       Asm->cmov(
-          SrcTy, Condition,
-          InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-              this->getDest()->getRegNum()),
+          SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
+                                this->getDest()->getRegNum()),
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar));
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-    Asm->cmov(SrcTy, Condition,
-              InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                  this->getDest()->getRegNum()),
+    Asm->cmov(SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
+                                    this->getDest()->getRegNum()),
               Mem->toAsmAddress(Asm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void InstX86Cmov<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 26 matching lines @@
 
 template <class Machine>
 void InstX86Cmpps<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
   assert(Condition < InstX86Base<Machine>::Traits::Cond::Cmpps_Invalid);
   // Assuming there isn't any load folding for cmpps, and vector constants are
   // not allowed in PNaCl.
   assert(llvm::isa<Variable>(this->getSrc(1)));
-  const auto SrcVar = llvm::cast<Variable>(this->getSrc(1));
+  const auto *SrcVar = llvm::cast<Variable>(this->getSrc(1));
   if (SrcVar->hasReg()) {
-    Asm->cmpps(InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
+    Asm->cmpps(InstX86Base<Machine>::Traits::getEncodedXmm(
                    this->getDest()->getRegNum()),
-               InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                   SrcVar->getRegNum()),
+               InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()),
                Condition);
   } else {
     typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(SrcVar);
-    Asm->cmpps(InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
+    Asm->cmpps(InstX86Base<Machine>::Traits::getEncodedXmm(
                    this->getDest()->getRegNum()),
                SrcStackAddr, Condition);
   }
 }
 
 template <class Machine>
 void InstX86Cmpps<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 28 matching lines @@
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Type Ty = this->getSrc(0)->getType();
   const auto Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   const typename InstX86Base<Machine>::Traits::Address Addr =
       Mem->toAsmAddress(Asm);
-  const auto VarReg = llvm::cast<Variable>(this->getSrc(2));
+  const auto *VarReg = llvm::cast<Variable>(this->getSrc(2));
   assert(VarReg->hasReg());
   const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          VarReg->getRegNum());
+      InstX86Base<Machine>::Traits::getEncodedGPR(VarReg->getRegNum());
   Asm->cmpxchg(Ty, Addr, Reg, this->Locked);
 }
 
 template <class Machine>
 void InstX86Cmpxchg<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   if (this->Locked) {
     Str << "lock ";
@@ skipping 80 matching lines @@
     static const typename InstX86Base<Machine>::Traits::Assembler::
         template CastEmitterRegOp<
             typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
             typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister>
             Emitter = {&InstX86Base<Machine>::Traits::Assembler::cvtsi2ss,
                        &InstX86Base<Machine>::Traits::Assembler::cvtsi2ss};
     emitIASCastRegOp<
         Machine,
         typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
         typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR>(
-        Func, DestTy, Dest, SrcTy, Src, Emitter);
+        InstX86Base<Machine>::Traits::getEncodedXmm,
+        InstX86Base<Machine>::Traits::getEncodedGPR>(Func, DestTy, Dest, SrcTy,
+                                                     Src, Emitter);
     return;
   }
   case Tss2si: {
     assert(isScalarFloatingType(SrcTy));
     assert(isScalarIntegerType(DestTy));
     if (!InstX86Base<Machine>::Traits::Is64Bit) {
       assert(typeWidthInBytes(DestTy) <= 4);
     } else {
       assert(DestTy == IceType_i32 || DestTy == IceType_i64);
     }
     static const typename InstX86Base<Machine>::Traits::Assembler::
         template CastEmitterRegOp<
             typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
             typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
             Emitter = {&InstX86Base<Machine>::Traits::Assembler::cvttss2si,
                        &InstX86Base<Machine>::Traits::Assembler::cvttss2si};
     emitIASCastRegOp<
         Machine,
         typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
         typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR,
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm>(
-        Func, DestTy, Dest, SrcTy, Src, Emitter);
+        InstX86Base<Machine>::Traits::getEncodedGPR,
+        InstX86Base<Machine>::Traits::getEncodedXmm>(Func, DestTy, Dest, SrcTy,
+                                                     Src, Emitter);
     return;
   }
   case Float2float: {
     assert(isScalarFloatingType(SrcTy));
     assert(isScalarFloatingType(DestTy));
     assert(DestTy != SrcTy);
     static const typename InstX86Base<
         Machine>::Traits::Assembler::XmmEmitterRegOp Emitter = {
         &InstX86Base<Machine>::Traits::Assembler::cvtfloat2float,
         &InstX86Base<Machine>::Traits::Assembler::cvtfloat2float};
@@ skipping 59 matching lines @@
   const Operand *Src1 = this->getSrc(1);
   Type Ty = Src0->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterRegOp
       RegEmitter = {&InstX86Base<Machine>::Traits::Assembler::cmp,
                     &InstX86Base<Machine>::Traits::Assembler::cmp,
                     &InstX86Base<Machine>::Traits::Assembler::cmp};
   static const typename InstX86Base<
       Machine>::Traits::Assembler::GPREmitterAddrOp AddrEmitter = {
       &InstX86Base<Machine>::Traits::Assembler::cmp,
       &InstX86Base<Machine>::Traits::Assembler::cmp};
-  if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
+  if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
       emitIASRegOpTyGPR<Machine>(Func, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   emitIASAsAddrOpTyGPR<Machine>(Func, Ty, Src0, Src1, AddrEmitter);
 }
 
 template <class Machine>
 void InstX86Icmp<Machine>::dump(const Cfg *Func) const {
@@ skipping 18 matching lines @@
   Str << ", ";
   this->getSrc(0)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Ucomiss<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   // Currently src0 is always a variable by convention, to avoid having two
   // memory operands.
   assert(llvm::isa<Variable>(this->getSrc(0)));
-  const auto Src0Var = llvm::cast<Variable>(this->getSrc(0));
+  const auto *Src0Var = llvm::cast<Variable>(this->getSrc(0));
   Type Ty = Src0Var->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       Emitter = {&InstX86Base<Machine>::Traits::Assembler::ucomiss,
                  &InstX86Base<Machine>::Traits::Assembler::ucomiss};
   emitIASRegOpTyXMM<Machine>(Func, Ty, Src0Var, this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Ucomiss<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 44 matching lines @@
   const Operand *Src1 = this->getSrc(1);
   Type Ty = Src0->getType();
   // The Reg/Addr form of test is not encodeable.
   static const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterRegOp
       RegEmitter = {&InstX86Base<Machine>::Traits::Assembler::test, nullptr,
                     &InstX86Base<Machine>::Traits::Assembler::test};
   static const typename InstX86Base<
       Machine>::Traits::Assembler::GPREmitterAddrOp AddrEmitter = {
       &InstX86Base<Machine>::Traits::Assembler::test,
       &InstX86Base<Machine>::Traits::Assembler::test};
-  if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
+  if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
       emitIASRegOpTyGPR<Machine>(Func, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   emitIASAsAddrOpTyGPR<Machine>(Func, Ty, Src0, Src1, AddrEmitter);
 }
 
 template <class Machine>
 void InstX86Test<Machine>::dump(const Cfg *Func) const {
@@ skipping 43 matching lines @@
 }
 
 template <class Machine>
 void InstX86Store<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   const Operand *Dest = this->getSrc(1);
   const Operand *Src = this->getSrc(0);
   Type DestTy = Dest->getType();
   if (isScalarFloatingType(DestTy)) {
     // Src must be a register, since Dest is a Mem operand of some kind.
-    const auto SrcVar = llvm::cast<Variable>(Src);
+    const auto *SrcVar = llvm::cast<Variable>(Src);
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-            SrcVar->getRegNum());
+        InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
     typename InstX86Base<Machine>::Traits::Assembler *Asm =
         Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
-    if (const auto DestVar = llvm::dyn_cast<Variable>(Dest)) {
+    if (const auto *DestVar = llvm::dyn_cast<Variable>(Dest)) {
       assert(!DestVar->hasReg());
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(DestVar));
       Asm->movss(DestTy, StackAddr, SrcReg);
     } else {
       const auto DestMem =
           llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
               Dest);
@@ skipping 34 matching lines @@
   this->getSrc(0)->emit(Func);
   Str << ", ";
   this->getSrc(1)->emit(Func);
 }
 
 template <class Machine>
 void InstX86StoreP<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
-  const auto SrcVar = llvm::cast<Variable>(this->getSrc(0));
+  const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
   const auto DestMem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(1));
   assert(DestMem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   assert(SrcVar->hasReg());
   Asm->movups(DestMem->toAsmAddress(Asm),
-              InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                  SrcVar->getRegNum()));
+              InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
 }
 
 template <class Machine>
 void InstX86StoreP<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storep." << this->getSrc(0)->getType() << " ";
   this->getSrc(1)->dump(Func);
   Str << ", ";
@@ skipping 13 matching lines @@
   this->getSrc(0)->emit(Func);
   Str << ", ";
   this->getSrc(1)->emit(Func);
 }
 
 template <class Machine>
 void InstX86StoreQ<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
-  const auto SrcVar = llvm::cast<Variable>(this->getSrc(0));
+  const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
   const auto DestMem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(1));
   assert(DestMem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   assert(SrcVar->hasReg());
   Asm->movq(DestMem->toAsmAddress(Asm),
-            InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                SrcVar->getRegNum()));
+            InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
 }
 
 template <class Machine>
 void InstX86StoreQ<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storeq." << this->getSrc(0)->getType() << " ";
   this->getSrc(1)->dump(Func);
   Str << ", ";
   this->getSrc(0)->dump(Func);
 }
 
 template <class Machine> void InstX86Lea<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   assert(this->getDest()->hasReg());
   Str << "\tleal\t";
   Operand *Src0 = this->getSrc(0);
-  if (const auto Src0Var = llvm::dyn_cast<Variable>(Src0)) {
+  if (const auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
     Type Ty = Src0Var->getType();
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
-    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty)->emit(Func);
+    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty, Variable::NoRegister)
+        ->emit(Func);
   } else {
     Src0->emit(Func);
   }
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 inline bool isIntegerConstant(const Operand *Op) {
   return llvm::isa<ConstantInteger32>(Op) || llvm::isa<ConstantInteger64>(Op);
 }
@@ skipping 23 matching lines @@
   // src. This works even for stack-allocated dest variables because
   // typeWidthOnStack() pads to a 4-byte boundary even if only a lower portion
   // is used.
   // TODO: This assert disallows usages such as copying a floating
   // point value between a vector and a scalar (which movss is used for). Clean
   // this up.
   assert(Func->getTarget()->typeWidthInBytesOnStack(DestTy) ==
          Func->getTarget()->typeWidthInBytesOnStack(SrcTy));
   Src->emit(Func);
   Str << ", ";
-  this->getDest()->asType(SrcTy)->emit(Func);
+  int32_t NewRegNum = Variable::NoRegister;
+  if (this->getDest()->hasReg())
+    NewRegNum = InstX86Base<Machine>::Traits::getGprForType(
+        SrcTy, this->getDest()->getRegNum());
+  const Variable *NewDest = SrcTy == DestTy
+                                ? this->getDest()
+                                : this->getDest()->asType(SrcTy, NewRegNum);
+  NewDest->emit(Func);
 }
 
 template <class Machine>
 void InstX86Mov<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   Type DestTy = Dest->getType();
   Type SrcTy = Src->getType();
   // Mov can be used for GPRs or XMM registers. Also, the type does not
@@ skipping 36 matching lines @@
       // when both Src and Dest are integer types.
       if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
           isIntegerConstant(Src)) {
         uint64_t Value = -1;
         if (const auto *C64 = llvm::dyn_cast<ConstantInteger64>(Src)) {
           Value = C64->getValue();
         } else {
           Value = llvm::cast<ConstantInteger32>(Src)->getValue();
         }
         Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>()
-            ->movabs(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                         Dest->getRegNum()),
-                     Value);
+            ->movabs(
+                InstX86Base<Machine>::Traits::getEncodedGPR(Dest->getRegNum()),
+                Value);
         return;
       }
       if (isScalarIntegerType(SrcTy)) {
         DestTy = SrcTy;
       }
       emitIASRegOpTyGPR<Machine>(Func, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
     // Dest must be Stack and Src *could* be a register. Use Src's type to
     // decide on the emitters.
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(Dest));
     if (isScalarFloatingType(SrcTy)) {
       // Src must be a register.
-      const auto SrcVar = llvm::cast<Variable>(Src);
+      const auto *SrcVar = llvm::cast<Variable>(Src);
       assert(SrcVar->hasReg());
       typename InstX86Base<Machine>::Traits::Assembler *Asm =
           Func->getAssembler<
               typename InstX86Base<Machine>::Traits::Assembler>();
-      Asm->movss(SrcTy, StackAddr,
-                 InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                     SrcVar->getRegNum()));
+      Asm->movss(SrcTy, StackAddr, InstX86Base<Machine>::Traits::getEncodedXmm(
+                                       SrcVar->getRegNum()));
       return;
     } else {
       // Src can be a register or immediate.
       assert(isScalarIntegerType(SrcTy));
       emitIASAddrOpTyGPR<Machine>(Func, SrcTy, StackAddr, Src, GPRAddrEmitter);
       return;
     }
     return;
   }
 }
 
 template <class Machine>
 void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
-  const auto SrcVar = llvm::cast<Variable>(this->getSrc(0));
+  const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
   // For insert/extract element (one of Src/Dest is an Xmm vector and the other
   // is an int type).
   if (SrcVar->getType() == IceType_i32 ||
       (InstX86Base<Machine>::Traits::Is64Bit &&
        SrcVar->getType() == IceType_i64)) {
     assert(isVectorType(Dest->getType()) ||
            (isScalarFloatingType(Dest->getType()) &&
             typeWidthInBytes(SrcVar->getType()) ==
                 typeWidthInBytes(Dest->getType())));
     assert(Dest->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-            Dest->getRegNum());
+        InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum());
     if (SrcVar->hasReg()) {
-      Asm->movd(SrcVar->getType(), DestReg,
-                InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                    SrcVar->getRegNum()));
+      Asm->movd(
+          SrcVar->getType(), DestReg,
+          InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum()));
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar));
       Asm->movd(SrcVar->getType(), DestReg, StackAddr);
     }
   } else {
     assert(isVectorType(SrcVar->getType()) ||
            (isScalarFloatingType(SrcVar->getType()) &&
             typeWidthInBytes(SrcVar->getType()) ==
                 typeWidthInBytes(Dest->getType())));
     assert(SrcVar->hasReg());
     assert(Dest->getType() == IceType_i32 ||
            (InstX86Base<Machine>::Traits::Is64Bit &&
             Dest->getType() == IceType_i64));
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-            SrcVar->getRegNum());
+        InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
     if (Dest->hasReg()) {
       Asm->movd(Dest->getType(),
-                InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-                    Dest->getRegNum()),
+                InstX86Base<Machine>::Traits::getEncodedGPR(Dest->getRegNum()),
                 SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(Dest));
       Asm->movd(Dest->getType(), StackAddr, SrcReg);
     }
   }
 }
@@ skipping 56 matching lines @@
   emitIASMovlikeXMM<Machine>(Func, Dest, Src, Emitter);
 }
 
 template <class Machine>
 void InstX86MovssRegs<Machine>::emitIAS(const Cfg *Func) const {
   // This is Binop variant is only intended to be used for reg-reg moves where
   // part of the Dest register is untouched.
   assert(this->getSrcSize() == 2);
   const Variable *Dest = this->getDest();
   assert(Dest == this->getSrc(0));
-  const auto SrcVar = llvm::cast<Variable>(this->getSrc(1));
+  const auto *SrcVar = llvm::cast<Variable>(this->getSrc(1));
   assert(Dest->hasReg() && SrcVar->hasReg());
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Asm->movss(IceType_f32,
-             InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                 Dest->getRegNum()),
-             InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                 SrcVar->getRegNum()));
+             InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum()),
+             InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
 }
 
 template <class Machine>
 void InstX86Movsx<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   // Dest must be a > 8-bit register, but Src can be 8-bit. In practice we just
   // use the full register for Dest to avoid having an OperandSizeOverride
   // prefix. It also allows us to only dispatch on SrcTy.
@@ skipping 39 matching lines @@
   Str << "nop (variant = " << Variant << ")";
 }
 
 template <class Machine> void InstX86Fld<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Type Ty = this->getSrc(0)->getType();
   SizeT Width = typeWidthInBytes(Ty);
-  const auto Var = llvm::dyn_cast<Variable>(this->getSrc(0));
+  const auto *Var = llvm::dyn_cast<Variable>(this->getSrc(0));
   if (Var && Var->hasReg()) {
     // This is a physical xmm register, so we need to spill it to a temporary
     // stack slot.
     Str << "\tsubl\t$" << Width << ", %esp"
         << "\n";
     Str << "\tmov"
         << InstX86Base<Machine>::Traits::TypeAttributes[Ty].SdSsString << "\t";
     Var->emit(Func);
     Str << ", (%esp)\n";
     Str << "\tfld" << this->getFldString(Ty) << "\t"
         << "(%esp)\n";
     Str << "\taddl\t$" << Width << ", %esp";
     return;
   }
   Str << "\tfld" << this->getFldString(Ty) << "\t";
   this->getSrc(0)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Fld<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Operand *Src = this->getSrc(0);
   Type Ty = Src->getType();
-  if (const auto Var = llvm::dyn_cast<Variable>(Src)) {
+  if (const auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->hasReg()) {
       // This is a physical xmm register, so we need to spill it to a temporary
       // stack slot.
       Immediate Width(typeWidthInBytes(Ty));
       Asm->sub(IceType_i32,
                InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
                Width);
       typename InstX86Base<Machine>::Traits::Address StackSlot =
           typename InstX86Base<Machine>::Traits::Address(
               InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, 0);
       Asm->movss(Ty, StackSlot,
-                 InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                     Var->getRegNum()));
+                 InstX86Base<Machine>::Traits::getEncodedXmm(Var->getRegNum()));
       Asm->fld(Ty, StackSlot);
       Asm->add(IceType_i32,
                InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
                Width);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(Var));
       Asm->fld(Ty, StackAddr);
     }
-  } else if (const auto Mem = llvm::dyn_cast<
+  } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     Asm->fld(Ty, Mem->toAsmAddress(Asm));
-  } else if (const auto Imm = llvm::dyn_cast<Constant>(Src)) {
+  } else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
     Asm->fld(Ty, InstX86Base<Machine>::Traits::Address::ofConstPool(Asm, Imm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine> void InstX86Fld<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 59 matching lines @@
     // Dest is a physical (xmm) register, so st(0) needs to go through memory.
     // Hack this by creating a temporary stack slot, spilling st(0) there,
     // loading it into the xmm register, and deallocating the stack slot.
     Immediate Width(typeWidthInBytes(Ty));
     Asm->sub(IceType_i32,
              InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, Width);
     typename InstX86Base<Machine>::Traits::Address StackSlot =
         typename InstX86Base<Machine>::Traits::Address(
             InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, 0);
     Asm->fstp(Ty, StackSlot);
-    Asm->movss(Ty, InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
-                       Dest->getRegNum()),
+    Asm->movss(Ty,
+               InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum()),
                StackSlot);
     Asm->add(IceType_i32,
              InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, Width);
   }
 }
 
 template <class Machine>
 void InstX86Fstp<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 44 matching lines @@
              .PackString << "\t";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   this->getSrc(0)->emit(Func);
   Str << ", ";
   Variable *Dest = this->getDest();
   // pextrw must take a register dest. There is an SSE4.1 version that takes a
   // memory dest, but we aren't using it. For uniformity, just restrict them
   // all to have a register dest for now.
   assert(Dest->hasReg());
-  Dest->asType(IceType_i32)->emit(Func);
+  Dest->asType(IceType_i32, Dest->getRegNum())->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pextr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   const Variable *Dest = this->getDest();
-  Type DispatchTy = Dest->getType();
+  Type DispatchTy = InstX86Base<Machine>::Traits::getInVectorElementType(
+      this->getSrc(0)->getType());
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Func->getTarget())
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   // pextrw must take a register dest. There is an SSE4.1 version that takes a
   // memory dest, but we aren't using it. For uniformity, just restrict them
   // all to have a register dest for now.
   assert(Dest->hasReg());
   // pextrw's Src(0) must be a register (both SSE4.1 and SSE2).
   assert(llvm::cast<Variable>(this->getSrc(0))->hasReg());
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::pextr, nullptr};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm>(
+      InstX86Base<Machine>::Traits::getEncodedGPR,
+      InstX86Base<Machine>::Traits::getEncodedXmm>(
       Func, DispatchTy, Dest, this->getSrc(0), this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Pinsr<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 3);
   // pinsrb and pinsrd are SSE4.1 instructions.
   assert(this->getDest()->getType() == IceType_v8i16 ||
          this->getDest()->getType() == IceType_v8i1 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Func->getTarget())
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   Str << "\t" << this->Opcode
       << InstX86Base<
              Machine>::Traits::TypeAttributes[this->getDest()->getType()]
              .PackString << "\t";
   this->getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = this->getSrc(1);
-  if (const auto Src1Var = llvm::dyn_cast<Variable>(Src1)) {
+  if (const auto *Src1Var = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
     if (Src1Var->hasReg()) {
-      Src1Var->asType(IceType_i32)->emit(Func);
+      int32_t NewRegNum =
+          InstX86Base<Machine>::Traits::getBaseReg(Src1Var->getRegNum());
+      const Variable *NewSrc = Src1Var->asType(IceType_i32, NewRegNum);
+      NewSrc->emit(Func);
     } else {
       Src1Var->emit(Func);
     }
   } else {
     Src1->emit(Func);
   }
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pinsr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
   // pinsrb and pinsrd are SSE4.1 instructions.
   const Operand *Src0 = this->getSrc(1);
   Type DispatchTy = Src0->getType();
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Func->getTarget())
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   // If src1 is a register, it should always be r32 (this should fall out from
   // the encodings for ByteRegs overlapping the encodings for r32), but we have
-  // to trust the regalloc to not choose "ah", where it doesn't overlap.
+  // to make sure the register allocator didn't choose an 8-bit high register
+  // like "ah".
+  if (BuildDefs::asserts()) {
+    if (auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
+      if (Src0Var->hasReg()) {
+        int32_t RegNum = Src0Var->getRegNum();
+        int32_t BaseRegNum = InstX86Base<Machine>::Traits::getBaseReg(RegNum);
+        (void)BaseRegNum;
+        assert(InstX86Base<Machine>::Traits::getEncodedGPR(RegNum) ==
+               InstX86Base<Machine>::Traits::getEncodedGPR(BaseRegNum));
+      }
+    }
+  }
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::pinsr,
                      &InstX86Base<Machine>::Traits::Assembler::pinsr};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR>(
+      InstX86Base<Machine>::Traits::getEncodedXmm,
+      InstX86Base<Machine>::Traits::getEncodedGPR>(
       Func, DispatchTy, this->getDest(), Src0, this->getSrc(2), Emitter);
 }
 
 template <class Machine>
 void InstX86Pshufd<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   const Variable *Dest = this->getDest();
   Type Ty = Dest->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::pshufd,
                      &InstX86Base<Machine>::Traits::Assembler::pshufd};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm>(
+      InstX86Base<Machine>::Traits::getEncodedXmm,
+      InstX86Base<Machine>::Traits::getEncodedXmm>(
       Func, Ty, Dest, this->getSrc(0), this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Shufps<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   const Variable *Dest = this->getDest();
   assert(Dest == this->getSrc(0));
   Type Ty = Dest->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::shufps,
                      &InstX86Base<Machine>::Traits::Assembler::shufps};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm>(
+      InstX86Base<Machine>::Traits::getEncodedXmm,
+      InstX86Base<Machine>::Traits::getEncodedXmm>(
       Func, Ty, Dest, this->getSrc(1), this->getSrc(2), Emitter);
 }
 
 template <class Machine> void InstX86Pop<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 0);
   Str << "\tpop\t";
   this->getDest()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pop<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 0);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (this->getDest()->hasReg()) {
-    Asm->popl(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
+    Asm->popl(InstX86Base<Machine>::Traits::getEncodedGPR(
         this->getDest()->getRegNum()));
   } else {
     Asm->popl(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(this->getDest()));
   }
 }
 
 template <class Machine> void InstX86Pop<Machine>::dump(const Cfg *Func) const {
@@ skipping 31 matching lines @@
   Str << "esp = sub.i32 esp, " << Amount;
 }
 
 template <class Machine>
 void InstX86Push<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   // Push is currently only used for saving GPRs.
-  const auto Var = llvm::cast<Variable>(this->getSrc(0));
+  const auto *Var = llvm::cast<Variable>(this->getSrc(0));
   assert(Var->hasReg());
   Str << "\tpush\t";
   Var->emit(Func);
 }
 
 template <class Machine>
 void InstX86Push<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   // Push is currently only used for saving GPRs.
-  const auto Var = llvm::cast<Variable>(this->getSrc(0));
+  const auto *Var = llvm::cast<Variable>(this->getSrc(0));
   assert(Var->hasReg());
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
-  Asm->pushl(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-      Var->getRegNum()));
+  Asm->pushl(InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum()));
 }
 
 template <class Machine>
 void InstX86Push<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "push." << this->getSrc(0)->getType() << " ";
   this->dumpSources(Func);
 }
@@ skipping 78 matching lines @@
 }
 
 template <class Machine>
 void InstX86Setcc<Machine>::emitIAS(const Cfg *Func) const {
   assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
   assert(this->getDest()->getType() == IceType_i1);
   assert(this->getSrcSize() == 0);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (this->getDest()->hasReg())
-    Asm->setcc(Condition,
-               InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteReg(
-                   this->getDest()->getRegNum()));
+    Asm->setcc(Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
+                              this->getDest()->getRegNum()));
   else
     Asm->setcc(
         Condition,
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
             Func->getTarget())
             ->stackVarToAsmOperand(this->getDest()));
   return;
 }
 
 template <class Machine>
@@ skipping 27 matching lines @@
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Type Ty = this->getSrc(0)->getType();
   const auto Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   const typename InstX86Base<Machine>::Traits::Address Addr =
       Mem->toAsmAddress(Asm);
-  const auto VarReg = llvm::cast<Variable>(this->getSrc(1));
+  const auto *VarReg = llvm::cast<Variable>(this->getSrc(1));
   assert(VarReg->hasReg());
   const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          VarReg->getRegNum());
+      InstX86Base<Machine>::Traits::getEncodedGPR(VarReg->getRegNum());
   Asm->xadd(Ty, Addr, Reg, this->Locked);
 }
 
 template <class Machine>
 void InstX86Xadd<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   if (this->Locked) {
     Str << "lock ";
@@ skipping 16 matching lines @@
 
 template <class Machine>
 void InstX86Xchg<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Type Ty = this->getSrc(0)->getType();
   const auto *VarReg1 = llvm::cast<Variable>(this->getSrc(1));
   assert(VarReg1->hasReg());
   const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg1 =
-      InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-          VarReg1->getRegNum());
+      InstX86Base<Machine>::Traits::getEncodedGPR(VarReg1->getRegNum());
 
   if (const auto *VarReg0 = llvm::dyn_cast<Variable>(this->getSrc(0))) {
     assert(VarReg0->hasReg());
     const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg0 =
-        InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
-            VarReg0->getRegNum());
+        InstX86Base<Machine>::Traits::getEncodedGPR(VarReg0->getRegNum());
     Asm->xchg(Ty, Reg0, Reg1);
     return;
   }
 
   const auto *Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   const typename InstX86Base<Machine>::Traits::Address Addr =
@@ skipping 61 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H