Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 589 matching lines @@
     const bool DestIsScalarFP = isScalarFloatingType(Dest->getType());
     const bool CoreVFPMove = isMoveBetweenCoreAndVFPRegisters(Dest, Src0);
     const char *LoadOpcode =
         DestIsVector ? "vld1" : (DestIsScalarFP ? "vldr" : "ldr");
     const char *RegMovOpcode =
         (DestIsVector || DestIsScalarFP || CoreVFPMove) ? "vmov" : "mov";
     const char *ActualOpcode = isMemoryAccess(Src0) ? LoadOpcode : RegMovOpcode;
     // when vmov{c}'ing, we need to emit a width string. Otherwise, the
     // assembler might be tempted to assume we want a vector vmov{c}, and that
     // is disallowed because ARM.
     const char *NoWidthString = "";

[Karl, 2015/10/27 16:13:18]

constexprs?

[Jim Stichnoth, 2015/10/27 19:14:09]

C++ compiler says no.

     const char *WidthString =
         isMemoryAccess(Src0)
             ? (DestIsVector ? ".64" : NoWidthString)
             : (!CoreVFPMove ? getVecWidthString(DestTy) : NoWidthString);
 
     Str << "\t" << ActualOpcode << getPredicate() << WidthString << "\t";
     Dest->emit(Func);
     Str << ", ";
     Src0->emit(Func);
   } else {
     Variable *Src0 = llvm::cast<Variable>(getSrc(0));
     assert(Src0->hasReg());
     const char *ActualOpcode =
         isVectorType(Src0->getType())
             ? "vst1"
             : (isScalarFloatingType(Src0->getType()) ? "vstr" : "str");
     const char *NoWidthString = "";

[Karl, 2015/10/27 16:13:19]

constexprs?

[Jim Stichnoth, 2015/10/27 19:14:09]

C++ compiler says no.

     const char *WidthString =
         isVectorType(Src0->getType()) ? ".64" : NoWidthString;
     Str << "\t" << ActualOpcode << getPredicate() << WidthString << "\t";
     Src0->emit(Func);
     Str << ", ";
     Dest->emit(Func);
   }
 }
 
 void InstARM32Mov::emitIASSingleDestSingleSource(const Cfg *Func) const {
@@ skipping 214 matching lines @@
 
 template <> void InstARM32Movw::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\t" << Opcode << getPredicate() << "\t";
   getDest()->emit(Func);
   Str << ", ";
   Constant *Src0 = llvm::cast<Constant>(getSrc(0));
-  if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src0)) {
+  if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src0)) {
     Str << "#:lower16:";
     CR->emitWithoutPrefix(Func->getTarget());
   } else {
     Src0->emit(Func);
   }
 }
 
 template <> void InstARM32Movt::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Variable *Dest = getDest();
   Constant *Src1 = llvm::cast<Constant>(getSrc(1));
   Str << "\t" << Opcode << getPredicate() << "\t";
   Dest->emit(Func);
   Str << ", ";
-  if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src1)) {
+  if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src1)) {
     Str << "#:upper16:";
     CR->emitWithoutPrefix(Func->getTarget());
   } else {
     Src1->emit(Func);
   }
 }
 
 void InstARM32Pop::emit(const Cfg *Func) const {
   // TODO(jpp): Improve FP register save/restore.
   if (!BuildDefs::dump())
@@ skipping 526 matching lines @@
 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 
 template class InstARM32ThreeAddrFP<InstARM32::Vadd>;
 template class InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 template class InstARM32ThreeAddrFP<InstARM32::Vmul>;
 template class InstARM32ThreeAddrFP<InstARM32::Vsub>;
 
 template class InstARM32TwoAddrGPR<InstARM32::Movt>;
 
 } // end of namespace Ice