Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceAssemblerX86Base.h

 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 97 matching lines @@
   llvm::SmallVector<intptr_t, 20> UnresolvedNearPositions;
 
   template <class> friend class AssemblerX86Base;
 };
 
 template <class Machine> class AssemblerX86Base : public Assembler {
   AssemblerX86Base(const AssemblerX86Base &) = delete;
   AssemblerX86Base &operator=(const AssemblerX86Base &) = delete;
 
 protected:
-  AssemblerX86Base(AssemblerKind Kind, GlobalContext *Ctx,
-                   bool use_far_branches)
-      : Assembler(Kind, Ctx) {
+  AssemblerX86Base(AssemblerKind Kind, bool use_far_branches)
+      : Assembler(Kind) {
     // This mode is only needed and implemented for MIPS and ARM.
     assert(!use_far_branches);
     (void)use_far_branches;
   }
 
 public:
   using Traits = MachineTraits<Machine>;
 
   ~AssemblerX86Base() override;
 
@@ skipping 150 matching lines @@
   void popl(const typename Traits::Address &address);
 
   template <typename T = Traits,
             typename = typename std::enable_if<T::HasPusha>::type>
   void pushal();
   template <typename T = Traits,
             typename = typename std::enable_if<T::HasPopa>::type>
   void popal();
 
   void setcc(typename Traits::Cond::BrCond condition,
-             typename Traits::ByteRegister dst);
+             typename Traits::GPRRegister dst);
   void setcc(typename Traits::Cond::BrCond condition,
              const typename Traits::Address &address);
 
   void mov(Type Ty, typename Traits::GPRRegister dst, const Immediate &src);
   void mov(Type Ty, typename Traits::GPRRegister dst,
            typename Traits::GPRRegister src);
   void mov(Type Ty, typename Traits::GPRRegister dst,
            const typename Traits::Address &src);
   void mov(Type Ty, const typename Traits::Address &dst,
            typename Traits::GPRRegister src);
@@ skipping 645 matching lines @@
   template <typename RegType, typename T = Traits>
   typename std::enable_if<!T::Is64Bit, typename T::GPRRegister>::type
   gprEncoding(const RegType Reg) {
     return static_cast<typename T::GPRRegister>(Reg);
   }
 
   template <typename RegType>
   bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) {
     static constexpr bool IsGPR =
         std::is_same<typename std::decay<RegType>::type,
-                     typename Traits::ByteRegister>::value ||
-        std::is_same<typename std::decay<RegType>::type,
                      typename Traits::GPRRegister>::value;
 
     return IsGPR && (Reg & 0x04) != 0 && (Reg & 0x08) == 0 &&
            isByteSizedType(Ty);
   }
 
   // assembleAndEmitRex is used for determining which (if any) rex prefix
   // should be emitted for the current instruction. It allows different types
   // for Reg and Rm because they could be of different types (e.g., in mov[sz]x
   // instructions.) If Addr is not nullptr, then Rm is ignored, and Rex.B is
@@ skipping 97 matching lines @@
   emitUint8(0x66);
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #include "IceAssemblerX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H