Add hybrid assembler concept to ARM assembler.

tests_lit/assembler/arm32/load-store.ll

Index: tests_lit/assembler/arm32/load-store.ll
diff --git a/tests_lit/assembler/arm32/load-store.ll b/tests_lit/assembler/arm32/load-store.ll
index c398de9c31303bda263e22715336f252b9f4586d..25c1e9453abb31ea7e24c0e5dd4f0bc68034ea1e 100644
--- a/tests_lit/assembler/arm32/load-store.ll
+++ b/tests_lit/assembler/arm32/load-store.ll
@@ -25,13 +25,13 @@ define internal i32 @add1ToR0(i32 %p) {
 ; IASM-NEXT:    .byte 0x4
 ; IASM-NEXT:    .byte 0x0
 ; IASM-NEXT:    .byte 0x8d
-; IASM-NEXT:    .byte 0xe5
+; IASM-NEXT:    .byte 0xe3
 
 ; ASM-NEXT:     ldr     r0, [sp, #4]
 ; IASM-NEXT:    .byte 0x4
 ; IASM-NEXT:    .byte 0x0
 ; IASM-NEXT:    .byte 0x9d
-; IASM-NEXT:    .byte 0xe5
+; IASM-NEXT:    .byte 0xe3
 
 ; ASM-NEXT:     add     r0, r0, #1
 ; IASM-NEXT:    .byte 0x1
@@ -43,13 +43,13 @@ define internal i32 @add1ToR0(i32 %p) {
 ; IASM-NEXT:    .byte 0x0
 ; IASM-NEXT:    .byte 0x0
 ; IASM-NEXT:    .byte 0x8d
-; IASM-NEXT:    .byte 0xe5
+; IASM-NEXT:    .byte 0xe3
 
 ; ASM-NEXT:     ldr     r0, [sp]
 ; IASM-NEXT:    .byte 0x0
 ; IASM-NEXT:    .byte 0x0
 ; IASM-NEXT:    .byte 0x9d
-; IASM-NEXT:    .byte 0xe5
+; IASM-NEXT:    .byte 0xe3
 
 ; ASM-NEXT:     add     sp, sp, #8
 ; IASM-NEXT:    .byte 0x8