Add hybrid assembler concept to ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 20 matching lines @@
 #include "IceConditionCodesARM32.h"
 #include "IceDefs.h"
 #include "IceFixups.h"
 #include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
 namespace Ice {
 namespace ARM32 {
 
+/// Extends a fixup to be a textual, instruction fixup. That is, it emits text
+/// containing an instruction. This class is used to implement unimplemented
+/// emitIAS methods, allowing them to generate compilable assembly code.
+class TextInstFixup : public AssemblerFixup {
+public:
+  TextInstFixup(const std::string &Message)
+      : AssemblerFixup(), Message(Message) {}
+  ~TextInstFixup() = default;
+  virtual size_t emit(GlobalContext *Ctx, RelocOffsetT OverrideOffset,
+                      bool isPcRel) const;
+
+private:
+  std::string Message;

[Jim Stichnoth, 2015/10/20 16:28:27]

Can/should this be const?

[Karl, 2015/10/20 21:29:31]

Done.

+};
+
 class AssemblerARM32 : public Assembler {
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
 public:
   explicit AssemblerARM32(GlobalContext *Ctx, bool use_far_branches = false)
       : Assembler(Asm_ARM32, Ctx) {
     // TODO(kschimpf): Add mode if needed when branches are handled.
     (void)use_far_branches;
   }
@@ skipping 33 matching lines @@
   }
 
   void bindCfgNodeLabel(SizeT NodeNumber) override {
     assert(!getPreliminary());
     Label *L = getOrCreateCfgNodeLabel(NodeNumber);
     this->bind(L);
   }
 
   bool fixupIsPCRel(FixupKind Kind) const override {
     (void)Kind;
-    llvm_unreachable("Not yet implemented.");
+    // TODO(kschimpf) Decide if we need this.
+    return false;
   }
 
   void bind(Label *label);
 
-  // List of instructions implemented by integrated assembler.
+  // List of instructions implemented by integrated assembler. Returns true
+  // if able to generate corresponding instruction from given arguments.
 
-  void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+  bool add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
-  void bkpt(uint16_t Imm16);
+  bool bkpt(uint16_t Imm16);
 
-  void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
+  bool ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
-  void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+  bool mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
-  void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
+  bool bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
 
-  void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
+  bool str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
-  void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+  bool sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
 
+  void emitTextInst(const std::string &Text);
+
 private:
   // A vector of pool-allocated x86 labels for CFG nodes.
   using LabelVector = std::vector<Label *>;
   LabelVector CfgNodeLabels;
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
   Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
     return getOrCreateLabel(NodeNumber, CfgNodeLabels);
   }
 
   void emitInst(uint32_t Value) { Buffer.emit<uint32_t>(Value); }
 
   // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type,
   // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3).
   void emitType01(CondARM32::Cond Cond, uint32_t Type, uint32_t Opcode,
                   bool SetCc, uint32_t Rn, uint32_t Rd, uint32_t imm12);
 
   // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
   // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that
   // Address is assumed to be defined by decodeAddress() in
   // IceAssemblerARM32.cpp.
   void emitMemOp(CondARM32::Cond Cond, uint32_t InstType, bool IsLoad,
                  bool IsByte, uint32_t Rt, uint32_t Address);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H