Handle branch relative to pc in ARM integrated assembler.

src/IceAssemblerARM32.h

Index: src/IceAssemblerARM32.h
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index b1329030b1c21e728918994efeb3c27c3b722020..e2a0404387c2978752688ee73cb06cff9caed52b 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -38,6 +38,12 @@
 namespace Ice {
 namespace ARM32 {
 
+/// Encoding of an ARM 32-bit instruction.
+using InstValueType = uint32_t;

[Jim Stichnoth, 2015/10/23 21:32:07]

You might consider shortening these to InstValueT and InstOffsetT, analogous to
Ice::SizeT.  Even shorter possibilities might be IValueT/IOffsetT or
ValueT/OffsetT.

[Karl, 2015/10/26 18:32:43]

ValueT appeared too easy to confuse with other possibilities. Used IValueT and
IOffsetT.

+
+/// An Offset value (+/-) used in an ARM 32-bit instruction.
+using InstOffsetType = int32_t;
+
 class AssemblerARM32 : public Assembler {
   AssemblerARM32() = delete;
   AssemblerARM32(const AssemblerARM32 &) = delete;
@@ -63,8 +69,8 @@ public:
   void alignFunction() override {
     const SizeT Align = 1 << getBundleAlignLog2Bytes();
     SizeT BytesNeeded = Utils::OffsetToAlignment(Buffer.getPosition(), Align);
-    constexpr uint32_t UndefinedInst = 0xe7fedef0; // udf #60896
-    constexpr SizeT InstSize = sizeof(int32_t);
+    constexpr InstValueType UndefinedInst = 0xe7fedef0; // udf #60896
+    constexpr SizeT InstSize = sizeof(InstValueType);
     assert(BytesNeeded % InstSize == 0);
     while (BytesNeeded > 0) {
       AssemblerBuffer::EnsureCapacity ensured(&Buffer);
@@ -94,7 +100,13 @@ public:
     return CfgNodeLabels[NodeNumber];
   }
 
-  void bindCfgNodeLabel(const CfgNode *Node) override;
+  Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
+    return getOrCreateLabel(NodeNumber, CfgNodeLabels);
+  }
+
+  Label *getOrCreateLocalLabel(SizeT Number) {
+    return getOrCreateLabel(Number, LocalLabels);
+  }
 
   void bindLocalLabel(SizeT Number) {
     Label *L = getOrCreateLocalLabel(Number);
@@ -115,6 +127,8 @@ public:
   void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
+  void b(Label *L, CondARM32::Cond Cond);
+
   void bkpt(uint16_t Imm16);
 
   void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
@@ -132,7 +146,8 @@ public:
     return Asm->getKind() == Asm_ARM32;
   }
 
-  void emitTextInst(const std::string &Text, SizeT InstSize = sizeof(uint32_t));
+  void emitTextInst(const std::string &Text,
+                    SizeT InstSize = sizeof(InstValueType));
 
 private:
   // A vector of pool-allocated x86 labels for CFG nodes.
@@ -142,26 +157,33 @@ private:
   LabelVector LocalLabels;
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
-  Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
-    return getOrCreateLabel(NodeNumber, CfgNodeLabels);
-  }
-  Label *getOrCreateLocalLabel(SizeT Number) {
-    return getOrCreateLabel(Number, LocalLabels);
-  }
 
-  void emitInst(uint32_t Value) { Buffer.emit<uint32_t>(Value); }
+  void bindCfgNodeLabel(const CfgNode *Node) override;
+
+  void emitInst(InstValueType Value) { Buffer.emit<InstValueType>(Value); }
 
   // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type,
   // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3).
-  void emitType01(CondARM32::Cond Cond, uint32_t Type, uint32_t Opcode,
-                  bool SetCc, uint32_t Rn, uint32_t Rd, uint32_t imm12);
+  void emitType01(CondARM32::Cond Cond, InstValueType Type,
+                  InstValueType Opcode, bool SetCc, InstValueType Rn,
+                  InstValueType Rd, InstValueType imm12);
+
+  void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link);
 
   // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
   // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that
   // Address is assumed to be defined by decodeAddress() in
   // IceAssemblerARM32.cpp.
-  void emitMemOp(CondARM32::Cond Cond, uint32_t InstType, bool IsLoad,
+  void emitMemOp(CondARM32::Cond Cond, InstValueType InstType, bool IsLoad,
                  bool IsByte, uint32_t Rt, uint32_t Address);
+
+  void emitBranch(Label *L, CondARM32::Cond, bool Link);
+
+  // Encodes The given Offset into the branch instruction Inst.
+  InstValueType encodeBranchOffset(InstOffsetType Offset, InstValueType Inst);
+
+  // Returns the offset encoded in the branch instruction Inst.
+  static InstOffsetType decodeBranchOffset(InstValueType Inst);
 };
 
 } // end of namespace ARM32