Add CMP(register) and CMP(Immediate) to ARM integerated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 155 matching lines @@
   // Unable to decode, value left undefined.
   CantDecode = 0,
   // Value is register found.
   DecodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   DecodedAsRotatedImm8,
   // i.e. 0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii is the offset.
-  DecodedAsImmRegOffset
+  DecodedAsImmRegOffset,
+  // Value is 32bit integer constant.
+  DecodedAsConstI32
 };
 
+// Sets Encoding to a rotated Imm8 encoding of Value, if possible.
+inline IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) {
+  assert(RotateAmt < (1 << kRotateBits));
+  assert(Immed8 < (1 << kImmed8Bits));
+  return (RotateAmt << kRotateShift) | (Immed8 << kImmed8Shift);
+}
+
 // Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
 // tt=Shift, and mmmm=Rm.
 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
                               IOffsetT imm5) {
   (void)kShiftImmBits;
   assert(imm5 < (1 << kShiftImmBits));
   return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
 }
 
 DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
       return DecodedAsRegister;
     }
   } else if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
     const IValueT Immed8 = FlexImm->getImm();
     const IValueT Rotate = FlexImm->getRotateAmt();
     if (!((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits))))
       return CantDecode;
     Value = (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
     return DecodedAsRotatedImm8;
   }
+  if (const auto *Const = llvm::dyn_cast<ConstantInteger32>(Opnd)) {
+    Value = Const->getValue();
+    return DecodedAsConstI32;
+  }
   return CantDecode;
 }
 
 IValueT decodeImmRegOffset(RegARM32::GPRRegister Reg, IOffsetT Offset,
                            OperandARM32Mem::AddrMode Mode) {
   IValueT Value = Mode | (encodeGPRRegister(Reg) << kRnShift);
   if (Offset < 0) {
     Value = (Value ^ U) | -Offset; // Flip U to adjust sign.
   } else {
     Value |= Offset;
@@ skipping 180 matching lines @@
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd,
                Src1Value);
     return;
   }
   case DecodedAsRotatedImm8: {
     // XXX (Immediate)
     //   xxx{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
     // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd,
                Src1Value);
     return;
   }
   }
 }
 
@@ skipping 70 matching lines @@
   // ADC (register) - ARM section 18.8.2, encoding A1:
   //   adc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // ADC (Immediate) - ARM section A8.8.1, encoding A1:
   //   adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+  // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Adc = B2 | B0; // 0101
   emitType01(Adc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 void AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // ADD (register) - ARM section A8.8.7, encoding A1:
   //   add{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
   // ADD (Sp plus register) - ARM section A8.8.11, encoding A1:
   //   add{s}<c> sp, <Rn>, <Rm>{, <shiff>}
   //
   // cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // ADD (Immediate) - ARM section A8.8.5, encoding A1:
   //   add{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   // ADD (SP plus immediate) - ARM section A8.8.9, encoding A1.
   //   add{s}<c> <Rd>, sp, #<RotatedImm8>
   //
   // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+  // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Add = B2; // 0100
   emitType01(Add, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 void AssemblerARM32::and_(const Operand *OpRd, const Operand *OpRn,
                           const Operand *OpSrc1, bool SetFlags,
                           CondARM32::Cond Cond) {
   // AND (register) - ARM section A8.8.14, encoding A1:
   //   and{s}<c> <Rd>, <Rn>{, <shift>}
   //
@@ skipping 31 matching lines @@
   // cccc000100101111111111110001mmmm where mmmm=rm and cccc=Cond.
   if (!(isGPRRegisterDefined(Rm) && isConditionDefined(Cond)))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
                            B21 | (0xfff << 8) | B4 |
                            (encodeGPRRegister(Rm) << kRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1,
+                         CondARM32::Cond Cond) {
+  IValueT Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  constexpr IValueT Cmp = B3 | B1; // ie. 1010
+  constexpr bool SetFlags = true;
+  constexpr IValueT Rd = RegARM32::Encoded_Reg_r0;
+  IValueT Src1Value;
+  // TODO(kschimpf) Other possible decodings of cmp.
+  switch (decodeOperand(OpSrc1, Src1Value)) {
+  default:
+    return setNeedsTextFixup();
+  case DecodedAsRegister: {
+    // CMP (register) - ARM section A8.8.38, encoding A1:
+    //   cmp<c> <Rn>, <Rm>{, <shift>}
+    //
+    // cccc00010101nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm,
+    // iiiii=Shift, and tt=ShiftKind.
+    constexpr IValueT Imm5 = 0;
+    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
+    emitType01(Cond, kInstTypeDataRegister, Cmp, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  case DecodedAsConstI32: {
+    // See if we can convert this to an CMP (immediate).
+    IValueT RotateAmt;
+    IValueT Imm8;
+    if (!OperandARM32FlexImm::canHoldImm(Src1Value, &RotateAmt, &Imm8))
+      return setNeedsTextFixup();
+    Src1Value = encodeRotatedImm8(RotateAmt, Imm8);
+    // Intentionally fall to next case!
+  }
+  case DecodedAsRotatedImm8: {
+    // CMP (immediate) - ARM section A8.8.37
+    //  cmp<c: <Rn>, #<RotatedImm8>
+    //
+    // cccc00110101nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+    emitType01(Cond, kInstTypeDataImmediate, Cmp, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  }
+  setNeedsTextFixup();
+}
+
 void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // EOR (register) - ARM section A*.8.47, encoding A1:
   //   eor{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000001snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // EOR (Immediate) - ARM section A8.*.46, encoding A1:
   //   eor{s}<c> <Rd>, <Rn>, #RotatedImm8
   //
   // cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+  // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Eor = B0; // 0001
   emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond) {
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Address;
@@ skipping 33 matching lines @@
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Src;
   // TODO(kschimpf) Handle other forms of mov.
   if (decodeOperand(OpSrc, Src) != DecodedAsRotatedImm8)
     return setNeedsTextFixup();
   // MOV (immediate) - ARM section A8.8.102, encoding A1:
   //   mov{S}<c> <Rd>, #<RotatedImm8>
   //
   // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd, and
-  // iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this assembler.
+  // iiiiiiiiiiii=Src defining RotatedImm8.  Note: We don't use movs in this
+  // assembler.
   constexpr bool SetFlags = false;
   if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
     // Conditions of rule violated.
     return setNeedsTextFixup();
   constexpr IValueT Rn = 0;
   constexpr IValueT Mov = B3 | B2 | B0; // 1101.
   emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src);
 }
 
 void AssemblerARM32::movw(const Operand *OpRd, const Operand *OpSrc,
@@ skipping 58 matching lines @@
   // SBC (register) - ARM section 18.8.162, encoding A1:
   //   sbc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // SBC (Immediate) - ARM section A8.8.161, encoding A1:
   //   sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
   // cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+  // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Sbc = B2 | B1; // 0110
   emitType01(Sbc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 void AssemblerARM32::sdiv(const Operand *OpRd, const Operand *OpRn,
                           const Operand *OpSrc1, CondARM32::Cond Cond) {
   // SDIV - ARM section A8.8.165, encoding A1.
   //   sdiv<c> <Rd>, <Rn>, <Rm>
   //
   // cccc01110001dddd1111mmmm0001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn, and
@@ skipping 154 matching lines @@
   //
   // cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiiii=shift, tt=ShiftKind, and s=SetFlags.
   //
   // Sub (Immediate) - ARM section A8.8.222, encoding A1:
   //    sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   // Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8
+  // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
   constexpr IValueT Sub = B1; // 0010
   emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice