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Side by Side Diff: src/DartARM32/assembler_arm.cc

Issue 1414483008: Add CMP(register) and CMP(Immediate) to ARM integerated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 5 years, 1 month ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #include "vm/globals.h" // NOLINT 9 #include "vm/globals.h" // NOLINT
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
(...skipping 248 matching lines...) Expand 10 before | Expand all | Expand 10 after
259 void Assembler::tst(Register rn, Operand o, Condition cond) { 259 void Assembler::tst(Register rn, Operand o, Condition cond) {
260 EmitType01(cond, o.type(), TST, 1, rn, R0, o); 260 EmitType01(cond, o.type(), TST, 1, rn, R0, o);
261 } 261 }
262 262
263 263
264 void Assembler::teq(Register rn, Operand o, Condition cond) { 264 void Assembler::teq(Register rn, Operand o, Condition cond) {
265 EmitType01(cond, o.type(), TEQ, 1, rn, R0, o); 265 EmitType01(cond, o.type(), TEQ, 1, rn, R0, o);
266 } 266 }
267 267
268 268
269 #if 0
270 // Moved to ARM32::AssemblerARM32::cmp()
269 void Assembler::cmp(Register rn, Operand o, Condition cond) { 271 void Assembler::cmp(Register rn, Operand o, Condition cond) {
270 EmitType01(cond, o.type(), CMP, 1, rn, R0, o); 272 EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
271 } 273 }
274 #endif
272 275
273 276
274 void Assembler::cmn(Register rn, Operand o, Condition cond) { 277 void Assembler::cmn(Register rn, Operand o, Condition cond) {
275 EmitType01(cond, o.type(), CMN, 1, rn, R0, o); 278 EmitType01(cond, o.type(), CMN, 1, rn, R0, o);
276 } 279 }
277 280
278 #if 0 281 #if 0
279 // Moved to ARM32::AssemberARM32::orr() 282 // Moved to ARM32::AssemberARM32::orr()
280 void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) { 283 void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) {
281 EmitType01(cond, o.type(), ORR, 0, rn, rd, o); 284 EmitType01(cond, o.type(), ORR, 0, rn, rd, o);
(...skipping 3392 matching lines...) Expand 10 before | Expand all | Expand 10 after
3674 3677
3675 3678
3676 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3679 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3677 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3680 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3678 return fpu_reg_names[reg]; 3681 return fpu_reg_names[reg];
3679 } 3682 }
3680 3683
3681 } // namespace dart 3684 } // namespace dart
3682 3685
3683 #endif // defined TARGET_ARCH_ARM 3686 #endif // defined TARGET_ARCH_ARM
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