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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1412923006: Add orr (register) and orr (immediate) to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
(...skipping 121 matching lines...) Expand 10 before | Expand all | Expand 10 after
132 void b(Label *L, CondARM32::Cond Cond); 132 void b(Label *L, CondARM32::Cond Cond);
133 133
134 void bkpt(uint16_t Imm16); 134 void bkpt(uint16_t Imm16);
135 135
136 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); 136 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
137 137
138 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); 138 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
139 139
140 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); 140 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
141 141
142 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
143 bool SetFlags, CondARM32::Cond Cond);
144
142 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 145 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
143 bool SetFlags, CondARM32::Cond Cond); 146 bool SetFlags, CondARM32::Cond Cond);
144 147
145 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); 148 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
146 149
147 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 150 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
148 bool SetFlags, CondARM32::Cond Cond); 151 bool SetFlags, CondARM32::Cond Cond);
149 152
150 static bool classof(const Assembler *Asm) { 153 static bool classof(const Assembler *Asm) {
151 return Asm->getKind() == Asm_ARM32; 154 return Asm->getKind() == Asm_ARM32;
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after
186 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); 189 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
187 190
188 // Returns the offset encoded in the branch instruction Inst. 191 // Returns the offset encoded in the branch instruction Inst.
189 static IOffsetT decodeBranchOffset(IValueT Inst); 192 static IOffsetT decodeBranchOffset(IValueT Inst);
190 }; 193 };
191 194
192 } // end of namespace ARM32 195 } // end of namespace ARM32
193 } // end of namespace Ice 196 } // end of namespace Ice
194 197
195 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 198 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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