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Side by Side Diff: tests_lit/assembler/arm32/add.ll

Issue 1411873002: emit add/sub registers instructions in integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 5 years, 2 months ago
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1 ; Show that we know how to translate add. 1 ; Show that we know how to translate add.
2 ; TODO(kschimpf) Currently only know how to test add 1 to R0.
3 2
4 ; NOTE: We use -O2 to get rid of memory stores. 3 ; NOTE: We use -O2 to get rid of memory stores.
5 4
Jim Stichnoth 2015/10/16 21:30:09 ; REQUIRES: allow_dump
Karl 2015/10/17 20:00:41 Done.
6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 5 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
7 ; RUN: | FileCheck %s --check-prefix=ASM 6 ; RUN: | FileCheck %s --check-prefix=ASM
8 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 7 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
9 ; RUN: | FileCheck %s --check-prefix=IASM 8 ; RUN: | FileCheck %s --check-prefix=IASM
10 9
11 define internal i32 @add1ToR0(i32 %p) { 10 define internal i32 @add1ToR0(i32 %p) {
12 %v = add i32 %p, 1 11 %v = add i32 %p, 1
13 ret i32 %v 12 ret i32 %v
14 } 13 }
15 14
16 ; ASM-LABEL: add1ToR0: 15 ; ASM-LABEL: add1ToR0:
17 ; ASM: add r0, r0, #1 16 ; ASM: add r0, r0, #1
18 ; ASM: bx lr 17 ; ASM-NEXT: bx lr
19 18
20 ; IASM-LABEL: add1ToR0: 19 ; IASM-LABEL: add1ToR0:
21 ; IASM: .byte 0x1 20 ; IASM: .byte 0x1
22 ; IASM-NEXT: .byte 0x0 21 ; IASM-NEXT: .byte 0x0
23 ; IASM-NEXT: .byte 0x80 22 ; IASM-NEXT: .byte 0x80
24 ; IASM-NEXT: .byte 0xe2 23 ; IASM-NEXT: .byte 0xe2
25 24
25 define internal i32 @Add2Regs(i32 %p1, i32 %p2) {
26 %v = add i32 %p1, %p2
27 ret i32 %v
28 }
29
30 ; ASM-LABEL: Add2Regs:
31 ; ASM: add r0, r0, r1
32 ; ASM-NEXT: bx lr
33
34 ; IASM-LABEL: Add2Regs:
35
36 ; IASM: .byte 0x1
37 ; IASM-NEXT: .byte 0x0
38 ; IASM-NEXT: .byte 0x80
39 ; IASM-NEXT: .byte 0xe0
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