Subzero. Misc ARM32 bugfixes.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 724 matching lines @@
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
     if (RegARM32::isI64RegisterPair(i)) {
       // We don't save register pairs explicitly. Instead, we rely on the code
       // fake-defing/fake-using each register in the pair.
       continue;
     }
     if (CalleeSaves[i] && RegsUsed[i]) {
       // TODO(jvoung): do separate vpush for each floating point register
       // segment and += 4, or 8 depending on type.
       ++NumCallee;
-      PreservedRegsSizeBytes += 4;
+      Variable *PhysicalRegister = getPhysicalRegister(i);
+      PreservedRegsSizeBytes +=
+          typeWidthInBytesOnStack(PhysicalRegister->getType());
       GPRsToPreserve.push_back(getPhysicalRegister(i));
     }
   }
   Ctx->statsUpdateRegistersSaved(NumCallee);
   if (!GPRsToPreserve.empty())
     _push(GPRsToPreserve);
 
   // Generate "mov FP, SP" if needed.
   if (UsesFramePointer) {
     Variable *FP = getPhysicalRegister(RegARM32::Reg_fp);
@@ skipping 865 matching lines @@
   // Dest->getType() is a non-i64 scalar.
   Variable *Src0R = legalizeToReg(Src0);
   Variable *T = makeReg(Dest->getType());
   // Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
   // difficult to determine (constant may be moved to a register).
   switch (Inst->getOp()) {
   default:
     break;
   case InstArithmetic::Udiv: {
-    constexpr bool IsRemainder = false;
+    constexpr bool NotRemainder = false;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_uxt, &TargetARM32::_udiv,
-                 H_udiv_i32, IsRemainder);
+                 H_udiv_i32, NotRemainder);
     return;
   }
   case InstArithmetic::Sdiv: {
-    constexpr bool IsRemainder = false;
+    constexpr bool NotRemainder = false;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_sxt, &TargetARM32::_sdiv,
-                 H_sdiv_i32, IsRemainder);
+                 H_sdiv_i32, NotRemainder);
     return;
   }
   case InstArithmetic::Urem: {
     constexpr bool IsRemainder = true;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_uxt, &TargetARM32::_udiv,
                  H_urem_i32, IsRemainder);
     return;
   }
   case InstArithmetic::Srem: {
     constexpr bool IsRemainder = true;
@@ skipping 73 matching lines @@
     Variable *Src1R = legalizeToReg(Src1RF);
     _mul(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Shl:
     _lsl(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Lshr:
+    if (Dest->getType() != IceType_i32) {
+      _uxt(Src0R, Src0R);
+    }
     _lsr(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Ashr:
+    if (Dest->getType() != IceType_i32) {
+      _sxt(Src0R, Src0R);
+    }
     _asr(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Udiv:
   case InstArithmetic::Sdiv:
   case InstArithmetic::Urem:
   case InstArithmetic::Srem:
     llvm_unreachable("Integer div/rem should have been handled earlier.");
     return;
   case InstArithmetic::Fadd:
@@ skipping 50 matching lines @@
 
 void TargetARM32::lowerBr(const InstBr *Inst) {
   if (Inst->isUnconditional()) {
     _br(Inst->getTargetUnconditional());
     return;
   }
   Operand *Cond = Inst->getCondition();
   // TODO(jvoung): Handle folding opportunities.
 
   Variable *Src0R = legalizeToReg(Cond);
+  assert(Src0R->mustHaveReg());
+  if (Src0R->getType() != IceType_i32)

[Jim Stichnoth, 2015/10/15 23:34:21]

Won't it always be the case that Src0R->getType() == IceType_i1 ?

[John, 2015/11/05 20:25:13]

maybe, but better safe than sorry. I left an assert for quick test failure, but
I left the if here.

+    _uxt(Src0R, Src0R);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0R, Zero);
   _br(Inst->getTargetTrue(), Inst->getTargetFalse(), CondARM32::NE);
 }
 
 void TargetARM32::lowerCall(const InstCall *Instr) {
   MaybeLeafFunc = false;
   NeedsStackAlignment = true;
 
   // Assign arguments to registers and stack. Also reserve stack.
@@ skipping 474 matching lines @@
     case IceType_i64: {
       // t0, t1 <- src0
       // dest[31..0]  = t0
       // dest[63..32] = t1
       assert(Src0->getType() == IceType_f64);
       auto *T = llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       T->initHiLo(Func);
       configureBitcastTemporary(T);
       Variable *Src0R = legalizeToReg(Src0);
       _mov(T, Src0R);
+      Context.insert(InstFakeUse::create(Func, T->getHi()));
+      Context.insert(InstFakeUse::create(Func, T->getLo()));
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_f64: {
       // T0 <- lo(src)
       // T1 <- hi(src)
       // vmov T2, T0, T1
       // Dest <- T2
       assert(Src0->getType() == IceType_i64);
       Variable *T = makeReg(DestType);
@@ skipping 930 matching lines @@
   Type Ty = Load->getDest()->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   Variable *DestLoad = Load->getDest();
 
   // TODO(jvoung): handled folding opportunities. Sign and zero extension can
   // be folded into a load.
   InstAssign *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
-void TargetARM32::doAddressOptLoad() {
-  UnimplementedError(Func->getContext()->getFlags());
-}
+void TargetARM32::doAddressOptLoad() {}
 
 void TargetARM32::randomlyInsertNop(float Probability,
                                     RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
   if (RNGW.getTrueWithProbability(Probability)) {
     UnimplementedError(Func->getContext()->getFlags());
   }
 }
 
 void TargetARM32::lowerPhi(const InstPhi * /*Inst*/) {
@@ skipping 50 matching lines @@
     Variable *T = makeReg(DestTy);
     Context.insert(InstFakeDef::create(Func, T));
     _mov(Dest, T);
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   // TODO(jvoung): handle folding opportunities.
   // cmp cond, #0; mov t, SrcF; mov_cond t, SrcT; mov dest, t
   Variable *CmpOpnd0 = legalizeToReg(Condition);
   Operand *CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
+  if (CmpOpnd0->getType() != IceType_i32)

[Jim Stichnoth, 2015/10/15 23:34:21]

Same comment as above -- isn't the type always IceType_i1?

[John, 2015/11/05 20:25:13]

Done.

+    _uxt(CmpOpnd0, CmpOpnd0);
   _cmp(CmpOpnd0, CmpOpnd1);
   static constexpr CondARM32::Cond Cond = CondARM32::NE;
   if (DestTy == IceType_i64) {
     SrcT = legalizeUndef(SrcT);
     SrcF = legalizeUndef(SrcF);
     // Set the low portion.
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Operand *SrcFLo = legalize(loOperand(SrcF), Legal_Reg | Legal_Flex);
     Variable *TLo = makeReg(SrcFLo->getType());
     _mov(TLo, SrcFLo);
@@ skipping 43 matching lines @@
     Variable *ValueHi = legalizeToReg(hiOperand(Value));
     Variable *ValueLo = legalizeToReg(loOperand(Value));
     _str(ValueHi, llvm::cast<OperandARM32Mem>(hiOperand(NewAddr)));
     _str(ValueLo, llvm::cast<OperandARM32Mem>(loOperand(NewAddr)));
   } else {
     Variable *ValueR = legalizeToReg(Value);
     _str(ValueR, NewAddr);
   }
 }
 
-void TargetARM32::doAddressOptStore() {
-  UnimplementedError(Func->getContext()->getFlags());
-}
+void TargetARM32::doAddressOptStore() {}
 
 void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
   if (Src0->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
     Variable *Src0Lo = legalizeToReg(loOperand(Src0));
     Variable *Src0Hi = legalizeToReg(hiOperand(Src0));
     for (SizeT I = 0; I < NumCases; ++I) {
       Operand *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
       Operand *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
       ValueLo = legalize(ValueLo, Legal_Reg | Legal_Flex);
       ValueHi = legalize(ValueHi, Legal_Reg | Legal_Flex);
       _cmp(Src0Lo, ValueLo);
       _cmp(Src0Hi, ValueHi, CondARM32::EQ);
       _br(Inst->getLabel(I), CondARM32::EQ);
     }
     _br(Inst->getLabelDefault());
     return;
   }
 
-  // 32 bit integer
   Variable *Src0Var = legalizeToReg(Src0);
+  // If Src0 is not an i32, we left shift it -- see the icmp lowering for the
+  // reason.
+  assert(Src0Var->mustHaveReg());
+  const size_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType());
+  assert(ShiftAmt < 32);
+  if (ShiftAmt > 0) {
+    Operand *ShiftConst = Ctx->getConstantInt32(ShiftAmt);
+    Variable *T = makeReg(IceType_i32);
+    _lsl(T, Src0Var, ShiftConst);
+    Src0Var = T;
+  }
+
   for (SizeT I = 0; I < NumCases; ++I) {
-    Operand *Value = Ctx->getConstantInt32(Inst->getValue(I));
+    Operand *Value = Ctx->getConstantInt32(Inst->getValue(I) << ShiftAmt);
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
     _br(Inst->getLabel(I), CondARM32::EQ);
   }
   _br(Inst->getLabelDefault());
 }
 
 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Inst*/) {
   _trap();
 }
@@ skipping 502 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice