Optimize 64-bit compares with zero

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2630 matching lines @@
     if (HasC2) {
       _br(Traits::TableFcmp[Index].C2, Label);
     }
     Constant *NonDefault =
         Ctx->getConstantInt32(!Traits::TableFcmp[Index].Default);
     _mov_redefined(Dest, NonDefault);
     Context.insert(Label);
   }
 }
 
+inline bool isZero(const Operand *Opnd) {
+  if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Opnd))
+    return C64->getValue() == 0;
+  if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(Opnd))
+    return C32->getValue() == 0;
+  return false;
+}
+
 template <class Machine>
 void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   Variable *Dest = Inst->getDest();
 
   if (isVectorType(Dest->getType())) {
     Type Ty = Src0->getType();
     // Promote i1 vectors to 128 bit integer vector types.
     if (typeElementType(Ty) == IceType_i1) {
@@ skipping 101 matching lines @@
     eliminateNextVectorSextInstruction(Dest);
     return;
   }
 
   if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
     lowerIcmp64(Inst);
     return;
   }
 
   // cmp b, c
+  if (isZero(Src1)) {
+    switch (Inst->getCondition()) {
+    default:
+      break;
+    case InstIcmp::Uge:
+      _mov(Dest, Ctx->getConstantInt(Dest->getType(), 1));
+      return;
+    case InstIcmp::Ult:
+      _mov(Dest, Ctx->getConstantInt(Dest->getType(), 0));
+      return;
+    }
+  }
   Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
   _cmp(Src0RM, Src1);
   _setcc(Dest, Traits::getIcmp32Mapping(Inst->getCondition()));
 }
 
 template <typename Machine>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, void>::type
 TargetX86Base<Machine>::lowerIcmp64(const InstIcmp *Inst) {
   // a=icmp cond, b, c ==> cmp b,c; a=1; br cond,L1; FakeUse(a); a=0; L1:
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   Variable *Dest = Inst->getDest();
   InstIcmp::ICond Condition = Inst->getCondition();
   size_t Index = static_cast<size_t>(Condition);
   assert(Index < Traits::TableIcmp64Size);
-  Operand *Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
-  Operand *Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
+  Constant *Zero = Ctx->getConstantZero(IceType_i32);
+  Constant *One = Ctx->getConstantInt32(1);
+  Operand *Src0LoRM = nullptr;
+  Operand *Src0HiRM = nullptr;
+  // Legalize the portions of Src0 that are going to be needed.
+  if (isZero(Src1)) {
+    switch (Condition) {
+    default:
+      llvm_unreachable("unexpected condition");
+      break;
+    // These two are not optimized, so we fall through to the general case,
+    // which needs the upper and lower halves legalized.
+    case InstIcmp::Sgt:
+    case InstIcmp::Sle:
+    // These four compare after performing an "or" of the high and low half, so they
+    // need the upper and lower halves legalized.
+    case InstIcmp::Eq:
+    case InstIcmp::Ule:
+    case InstIcmp::Ne:
+    case InstIcmp::Ugt:
+      Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
+    // These two test only the high half's sign bit, so they need only
+    // the upper half legalized.
+    case InstIcmp::Sge:
+    case InstIcmp::Slt:
+      Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
+      break;
+
+    // These two move constants and hence need no legalization.
+    case InstIcmp::Uge:
+    case InstIcmp::Ult:
+      break;
+    }
+  } else {
+    Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
+    Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
+  }
+  // Optimize comparisons with zero.
+  if (isZero(Src1)) {
+    Constant *SignMask = Ctx->getConstantInt32(0x80000000);
+    Variable *Temp = nullptr;
+    switch (Condition) {
+    default:
+      llvm_unreachable("unexpected condition");
+      break;
+    case InstIcmp::Eq:
+    case InstIcmp::Ule:
+      _mov(Temp, Src0LoRM);
+      _or(Temp, Src0HiRM);
+      Context.insert(InstFakeUse::create(Func, Temp));
+      _setcc(Dest, Traits::Cond::Br_e);
+      return;
+    case InstIcmp::Ne:
+    case InstIcmp::Ugt:
+      _mov(Temp, Src0LoRM);
+      _or(Temp, Src0HiRM);
+      Context.insert(InstFakeUse::create(Func, Temp));
+      _setcc(Dest, Traits::Cond::Br_ne);
+      return;
+    case InstIcmp::Uge:
+      _mov(Dest, Ctx->getConstantInt(Dest->getType(), 1));
+      return;
+    case InstIcmp::Ult:
+      _mov(Dest, Ctx->getConstantInt(Dest->getType(), 0));
+      return;
+    case InstIcmp::Sgt:
+      break;
+    case InstIcmp::Sge:
+      _test(Src0HiRM, SignMask);
+      _setcc(Dest, Traits::Cond::Br_e);
+      return;
+    case InstIcmp::Slt:
+      _test(Src0HiRM, SignMask);
+      _setcc(Dest, Traits::Cond::Br_ne);
+      return;
+    case InstIcmp::Sle:
+      break;
+    }
+  }
+  // Handle general compares.
   Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
   Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
-  Constant *Zero = Ctx->getConstantZero(IceType_i32);
-  Constant *One = Ctx->getConstantInt32(1);
   typename Traits::Insts::Label *LabelFalse =
       Traits::Insts::Label::create(Func, this);
   typename Traits::Insts::Label *LabelTrue =
       Traits::Insts::Label::create(Func, this);
   _mov(Dest, One);
   _cmp(Src0HiRM, Src1HiRI);
   if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
     _br(Traits::TableIcmp64[Index].C1, LabelTrue);
   if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
     _br(Traits::TableIcmp64[Index].C2, LabelFalse);
@@ skipping 2705 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H