Optimize 64-bit compares with zero

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 1754 matching lines @@
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},
 
+define internal void @icmpEqZero64Imm() {
+entry:
+  %cmp = icmp eq i64 123, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  call void @func()
+  br label %if.end
+
+if.end:                                          ; preds = %if.then, %if.end
+  ret void
+}
+; The following checks are not strictly necessary since one of the RUN
+; lines actually runs the output through the assembler.
+; CHECK-LABEL: icmpEqZero64Imm
+; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
+; OPTM1-LABEL: icmpEqZero64Imm
+; OPTM1-LABEL-NOT: cmp 0x{{[0-9a-f]+}},
+; ARM32-LABEL: icmpEqZero64Imm
+; ARM32-NOT: cmp #{{[0-9a-f]+}},
+
 define internal i64 @phi64Imm(i32 %x, i64 %y, i64 %z) {
 entry:
   %cond = icmp eq i32 %x, 88
   br i1 %cond, label %branch1, label %branch2
 branch1:
   %tmp = add i64 %y, %z
   br label %branch2
 
 branch2:
   %merge = phi i64 [ %tmp, %branch1 ], [ 20014547621496, %entry ]
@@ skipping 25 matching lines @@
 ; CHECK-LABEL: phi64Undef
 ; CHECK: mov {{.*}},0x0
 ; CHECK: mov {{.*}},0x0
 ; OPTM1-LABEL: phi64Undef
 ; OPTM1: mov {{.*}},0x0
 ; OPTM1: mov {{.*}},0x0
 ; ARM32-LABEL: phi64Undef
 ; ARM32: mov {{.*}} #0
 ; ARM32: mov {{.*}} #0