Subzero: Various fixes in preparation for x86-32 register aliasing.

src/IceTargetLoweringX8632.cpp

Index: src/IceTargetLoweringX8632.cpp
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index efadb85558a0844062e835138c1afc9d4ae6320b..dfb42d8392ec5105284990bc10aba62a5dbc26fc 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -436,8 +436,16 @@ void TargetX8632::addProlog(CfgNode *Node) {
   // Add push instructions for preserved registers.
   uint32_t NumCallee = 0;
   size_t PreservedRegsSizeBytes = 0;
+  llvm::SmallBitVector Pushed(CalleeSaves.size());
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
+    // SizeT Canonical = RegX8632::getCanonicalReg(i); // TODO(stichnot)
+    SizeT Canonical = i;
     if (CalleeSaves[i] && RegsUsed[i]) {
+      Pushed[Canonical] = true;
+    }
+  }
+  for (SizeT i = 0; i < Pushed.size(); ++i) {
+    if (Pushed[i]) {
       ++NumCallee;
       PreservedRegsSizeBytes += typeWidthInBytes(IceType_i32);
       _push(getPhysicalRegister(i));
@@ -601,11 +609,19 @@ void TargetX8632::addEpilog(CfgNode *Node) {
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
+  llvm::SmallBitVector Popped(CalleeSaves.size());
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
-    SizeT j = CalleeSaves.size() - i - 1;
+    // SizeT Canonical = RegX8632::getCanonicalReg(i); // TODO(stichnot)

[Karl, 2015/10/15 17:05:27]

I believe that John ran into this problem (not using canonical) this morning in
ARM.

+    SizeT Canonical = i;
+    if (CalleeSaves[i] && RegsUsed[i]) {
+      Popped[Canonical] = true;
+    }
+  }
+  for (SizeT i = 0; i < Popped.size(); ++i) {
+    SizeT j = Popped.size() - i - 1;
     if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame)
       continue;
-    if (CalleeSaves[j] && RegsUsed[j]) {
+    if (Popped[j]) {
       _pop(getPhysicalRegister(j));
     }
   }