Add MOV (register) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 607 matching lines @@
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
 }
 
 void AssemblerARM32::mov(const Operand *OpRd, const Operand *OpSrc,
                          CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Src;
   // TODO(kschimpf) Handle other forms of mov.
-  if (decodeOperand(OpSrc, Src) != DecodedAsRotatedImm8)
-    return setNeedsTextFixup();
-  // MOV (immediate) - ARM section A8.8.102, encoding A1:
-  //   mov{S}<c> <Rd>, #<RotatedImm8>
-  //
-  // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd, and
-  // iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this assembler.
   constexpr bool SetFlags = false;
-  if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
-    // Conditions of rule violated.
-    return setNeedsTextFixup();
   constexpr IValueT Rn = 0;
   constexpr IValueT Mov = B3 | B2 | B0; // 1101.
-  emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src);
+  switch (decodeOperand(OpSrc, Src)) {
+  default:

[Jim Stichnoth, 2015/10/30 21:47:02]

Do you mean for the default case to fallthrough?

[Karl, 2015/10/30 22:15:31]

Hmm, must be inhaling too many fumes. Fixing to require text fixup.

+  case DecodedAsRegister: {
+    // MOV (register) - ARM section A8.8.104, encoding A1:
+    //   mov{S}<c> <Rd>, <Rn>
+    //
+    // cccc0001101s0000dddd00000000mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
+    // and nnnn=Rn.
+    return setNeedsTextFixup();

[Jim Stichnoth, 2015/10/30 21:47:02]

The code below this is unreachable...

[Karl, 2015/10/30 22:15:31]

Apparently here is where I misplaced the default code. Removing.

+    if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataRegister, Mov, SetFlags, Rn, Rd, Src);
+    return;
+  }
+  case DecodedAsRotatedImm8: {
+    // MOV (immediate) - ARM section A8.8.102, encoding A1:
+    //   mov{S}<c> <Rd>, #<RotatedImm8>
+    //
+    // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd,
+    // and iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this
+    // assembler.
+    if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src);
+    return;
+  }
+  }
 }
 
 void AssemblerARM32::movw(const Operand *OpRd, const Operand *OpSrc,
                           CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc);
   if (Src == nullptr)
     return setNeedsTextFixup();
@@ skipping 209 matching lines @@
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8
   constexpr IValueT Sub = B1; // 0010
   emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice