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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1402403002: Handle stack spills in ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 5 years, 2 months ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
(...skipping 85 matching lines...) Expand 10 before | Expand all | Expand 10 after
96 96
97 void bind(Label *label); 97 void bind(Label *label);
98 98
99 // List of instructions implemented by integrated assembler. 99 // List of instructions implemented by integrated assembler.
100 100
101 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 101 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
102 bool SetFlags, CondARM32::Cond Cond); 102 bool SetFlags, CondARM32::Cond Cond);
103 103
104 void bkpt(uint16_t Imm16); 104 void bkpt(uint16_t Imm16);
105 105
106 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
107
106 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); 108 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
107 109
108 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); 110 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
109 111
112 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
113
110 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 114 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
111 bool SetFlags, CondARM32::Cond Cond); 115 bool SetFlags, CondARM32::Cond Cond);
112 116
113 static bool classof(const Assembler *Asm) { 117 static bool classof(const Assembler *Asm) {
114 return Asm->getKind() == Asm_ARM32; 118 return Asm->getKind() == Asm_ARM32;
115 } 119 }
116 120
117 private: 121 private:
118 // A vector of pool-allocated x86 labels for CFG nodes. 122 // A vector of pool-allocated x86 labels for CFG nodes.
119 using LabelVector = std::vector<Label *>; 123 using LabelVector = std::vector<Label *>;
120 LabelVector CfgNodeLabels; 124 LabelVector CfgNodeLabels;
121 125
122 Label *getOrCreateLabel(SizeT Number, LabelVector &Labels); 126 Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
123 Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) { 127 Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
124 return getOrCreateLabel(NodeNumber, CfgNodeLabels); 128 return getOrCreateLabel(NodeNumber, CfgNodeLabels);
125 } 129 }
126 130
127 void emitInst(uint32_t Value) { Buffer.emit<uint32_t>(Value); } 131 void emitInst(uint32_t Value) { Buffer.emit<uint32_t>(Value); }
128 132
129 // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type, 133 // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type,
130 // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3). 134 // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3).
131 void emitType01(CondARM32::Cond Cond, uint32_t Type, uint32_t Opcode, 135 void emitType01(CondARM32::Cond Cond, uint32_t Type, uint32_t Opcode,
132 bool SetCc, uint32_t Rn, uint32_t Rd, uint32_t imm12); 136 bool SetCc, uint32_t Rn, uint32_t Rd, uint32_t imm12);
137
138 // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
139 // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that
140 // Address is assumed to be defined by decodeAddress() in
141 // IceAssemblerARM32.cpp.
142 void emitMemOp(CondARM32::Cond Cond, uint32_t InstType, bool IsLoad,
143 bool IsByte, uint32_t Rt, uint32_t Address);
133 }; 144 };
134 145
135 } // end of namespace ARM32 146 } // end of namespace ARM32
136 } // end of namespace Ice 147 } // end of namespace Ice
137 148
138 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 149 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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