Handle stack spills in ARM integrated assembler.

src/DartARM32/assembler_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #ifndef VM_ASSEMBLER_ARM_H_
 #define VM_ASSEMBLER_ARM_H_
@@ skipping 122 matching lines @@
   }
 
   // Data-processing operands - Immediate.
   explicit Operand(uint32_t immediate) {
     ASSERT(immediate < (1 << kImmed8Bits));
     type_ = 1;
     encoding_ = immediate;
   }
 
 #if 0
-  // Moved to decode in IceAssemblerARM32.cpp
+  // Moved to decodeOperand() in IceAssemblerARM32.cpp
   // Data-processing operands - Rotated immediate.
   Operand(uint32_t rotate, uint32_t immed8) {
     ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits)));
     type_ = 1;
     encoding_ = (rotate << kRotateShift) | (immed8 << kImmed8Shift);
   }
 #endif
 
 #if 0
-  // Moved to decode in IceAssemblerARM32.cpp
+  // Moved to decodeOperand() in IceAssemblerARM32.cpp
   // Data-processing operands - Register.
   explicit Operand(Register rm) {
     type_ = 0;
     encoding_ = static_cast<uint32_t>(rm);
   }
 #endif
 
   // Data-processing operands - Logical shift/rotate by immediate.
   Operand(Register rm, Shift shift, uint32_t shift_imm) {
     ASSERT(shift_imm < (1 << kShiftImmBits));
@@ skipping 106 matching lines @@
   Address& operator=(const Address& other) {
     encoding_ = other.encoding_;
     kind_ = other.kind_;
     return *this;
   }
 
   bool Equals(const Address& other) const {
     return (encoding_ == other.encoding_) && (kind_ == other.kind_);
   }
 
+#if 0
+  // Moved to decodeImmRegOffset() in IceAssemblerARM32.cpp.
+  // Used to model stack offsets.
   explicit Address(Register rn, int32_t offset = 0, Mode am = Offset) {
     ASSERT(Utils::IsAbsoluteUint(12, offset));
     kind_ = Immediate;
     if (offset < 0) {
       encoding_ = (am ^ (1 << kUShift)) | -offset;  // Flip U to adjust sign.
     } else {
       encoding_ = am | offset;
     }
     encoding_ |= static_cast<uint32_t>(rn) << kRnShift;
   }
+#endif
 
   // There is no register offset mode unless Mode is Offset, in which case the
   // shifted register case below should be used.
   Address(Register rn, Register r, Mode am);
 
   Address(Register rn, Register rm,
           Shift shift = LSL, uint32_t shift_imm = 0, Mode am = Offset) {
     Operand o(rm, shift, shift_imm);
 
     if ((shift == LSL) && (shift_imm == 0)) {
@@ skipping 133 matching lines @@
 
   static const char* RegisterName(Register reg);
 
   static const char* FpuRegisterName(FpuRegister reg);
 
   // Data-processing instructions.
   void and_(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void eor(Register rd, Register rn, Operand o, Condition cond = AL);
 
+#if 0
+  // Moved to ARM32::AssemberARM32::sub()
   void sub(Register rd, Register rn, Operand o, Condition cond = AL);
   void subs(Register rd, Register rn, Operand o, Condition cond = AL);
+#endif
 
   void rsb(Register rd, Register rn, Operand o, Condition cond = AL);
   void rsbs(Register rd, Register rn, Operand o, Condition cond = AL);
 
 #if 0
-  // Moved to IceAssemblerARM32::mov
+  // Moved to ARM32::AssemblerARM32::add()
   void add(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void adds(Register rd, Register rn, Operand o, Condition cond = AL);
 #endif
 
   void adc(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void adcs(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void sbc(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void sbcs(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void rsc(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void tst(Register rn, Operand o, Condition cond = AL);
 
   void teq(Register rn, Operand o, Condition cond = AL);
 
   void cmp(Register rn, Operand o, Condition cond = AL);
 
   void cmn(Register rn, Operand o, Condition cond = AL);
 
   void orr(Register rd, Register rn, Operand o, Condition cond = AL);
   void orrs(Register rd, Register rn, Operand o, Condition cond = AL);
 
 #if 0
-  // Moved to IceAssemblerARM32::mov
+  // Moved to IceAssemblerARM32::mov()
   void mov(Register rd, Operand o, Condition cond = AL);
   void movs(Register rd, Operand o, Condition cond = AL);
 #endif
 
   void bic(Register rd, Register rn, Operand o, Condition cond = AL);
   void bics(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void mvn(Register rd, Operand o, Condition cond = AL);
   void mvns(Register rd, Operand o, Condition cond = AL);
 
@@ skipping 18 matching lines @@
 
   // Emulation of this instruction uses IP and the condition codes. Therefore,
   // none of the registers can be IP, and the instruction can only be used
   // unconditionally.
   void umaal(Register rd_lo, Register rd_hi, Register rn, Register rm);
 
   // Division instructions.
   void sdiv(Register rd, Register rn, Register rm, Condition cond = AL);
   void udiv(Register rd, Register rn, Register rm, Condition cond = AL);
 
+#if 0
+  // Moved to AssemblerARM32::ldr()
   // Load/store instructions.
   void ldr(Register rd, Address ad, Condition cond = AL);
+  // Moved to AssemblerARM32::str()
   void str(Register rd, Address ad, Condition cond = AL);
 
+  // Moved to AssemblerARM32::ldr()
   void ldrb(Register rd, Address ad, Condition cond = AL);
+  // Moved to AssemblerARM32::str()
   void strb(Register rd, Address ad, Condition cond = AL);
+#endif
 
   void ldrh(Register rd, Address ad, Condition cond = AL);
   void strh(Register rd, Address ad, Condition cond = AL);
 
   void ldrsb(Register rd, Address ad, Condition cond = AL);
   void ldrsh(Register rd, Address ad, Condition cond = AL);
 
   // ldrd and strd actually support the full range of addressing modes, but
   // we don't use them, and we need to split them up into two instructions for
   // ARMv5TE, so we only support the base + offset mode.
   void ldrd(Register rd, Register rn, int32_t offset, Condition cond = AL);
   void strd(Register rd, Register rn, int32_t offset, Condition cond = AL);
 
   void ldm(BlockAddressMode am, Register base,
            RegList regs, Condition cond = AL);
   void stm(BlockAddressMode am, Register base,
            RegList regs, Condition cond = AL);
 
   void ldrex(Register rd, Register rn, Condition cond = AL);
   void strex(Register rd, Register rt, Register rn, Condition cond = AL);
 
   // Miscellaneous instructions.
   void clrex();
   void nop(Condition cond = AL);
 
 #if 0
-  // Moved to: ARM32::AssemblerARM32.
+  // Moved to: ARM32::AssemblerARM32::bkpt()
   // Note that gdb sets breakpoints using the undefined instruction 0xe7f001f0.
   void bkpt(uint16_t imm16);
 
   static int32_t BkptEncoding(uint16_t imm16) {
     // bkpt requires that the cond field is AL.
     return (AL << kConditionShift) | B24 | B21 |
            ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf);
   }
 #endif
 
@@ skipping 110 matching lines @@
   void vtbl(DRegister dd, DRegister dn, int length, DRegister dm);
 
   // The words of qd and qm are interleaved with the low words of the result
   // in qd and the high words in qm.
   void vzipqw(QRegister qd, QRegister qm);
 
   // Branch instructions.
   void b(Label* label, Condition cond = AL);
   void bl(Label* label, Condition cond = AL);
 #if 0
-  // Moved to: ARM32::AssemblerARM32.
+  // Moved to: ARM32::AssemblerARM32::bx()
   void bx(Register rm, Condition cond = AL);
 #endif
   void blx(Register rm, Condition cond = AL);
 
   void Branch(const StubEntry& stub_entry,
               Patchability patchable = kNotPatchable,
               Register pp = PP,
               Condition cond = AL);
 
   void BranchLink(const StubEntry& stub_entry,
@@ skipping 399 matching lines @@
 
   bool constant_pool_allowed_;
 
   void LoadObjectHelper(Register rd,
                         const Object& object,
                         Condition cond,
                         bool is_unique,
                         Register pp);
 
 #if 0
-  // Moved to class AssemblerARM32.
+  // Moved to ARM32::AssemblerARM32::emitType01()
   void EmitType01(Condition cond,
                   int type,
                   Opcode opcode,
                   int set_cc,
                   Register rn,
                   Register rd,
                   Operand o);
 #endif
 
   void EmitType5(Condition cond, int32_t offset, bool link);
 
+#if 0
+  // Moved to ARM32::AssemberARM32::emitMemOp()
   void EmitMemOp(Condition cond,
                  bool load,
                  bool byte,
                  Register rd,
                  Address ad);
+#endif
 
   void EmitMemOpAddressMode3(Condition cond,
                              int32_t mode,
                              Register rd,
                              Address ad);
 
   void EmitMultiMemOp(Condition cond,
                       BlockAddressMode am,
                       bool load,
                       Register base,
@@ skipping 100 matching lines @@
                      Register new_value,
                      FieldContent old_content);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM_H_